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Message-ID: <9da1e9bf-0b3e-481e-a9c5-016238ee93ca@linaro.org>
Date: Tue, 23 Jan 2024 13:15:02 +0100
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Subject: Re: [PATCH V2] dt-bindings: clock: support NXP i.MX95
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To: "Peng Fan (OSS)" <peng.fan@oss.nxp.com>, robh+dt@kernel.org,
 krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, abelvesa@kernel.org,
 mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org,
 s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com
Cc: devicetree@vger.kernel.org, linux-imx@nxp.com, linux-clk@vger.kernel.org,
 linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
 Peng Fan <peng.fan@nxp.com>
References: <20240122013239.1434383-1-peng.fan@oss.nxp.com>
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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In-Reply-To: <20240122013239.1434383-1-peng.fan@oss.nxp.com>
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On 22/01/2024 02:32, Peng Fan (OSS) wrote:
> +
> +/* The index should match i.MX95 SCMI Firmware */
> +#define IMX95_CLK_32K                       1
> +#define IMX95_CLK_24M                       2
> +#define IMX95_CLK_FRO                       3
> +#define IMX95_CLK_SYSPLL1_VCO               4
> +#define IMX95_CLK_SYSPLL1_PFD0_UNGATED      5
> +#define IMX95_CLK_SYSPLL1_PFD0              6
> +#define IMX95_CLK_SYSPLL1_PFD0_DIV2         7
> +#define IMX95_CLK_SYSPLL1_PFD1_UNGATED      8
> +#define IMX95_CLK_SYSPLL1_PFD1              9
> +#define IMX95_CLK_SYSPLL1_PFD1_DIV2         10
> +#define IMX95_CLK_SYSPLL1_PFD2_UNGATED      11
> +#define IMX95_CLK_SYSPLL1_PFD2              12
> +#define IMX95_CLK_SYSPLL1_PFD2_DIV2         13
> +#define IMX95_CLK_AUDIOPLL1_VCO             14
> +#define IMX95_CLK_AUDIOPLL1                 15
> +#define IMX95_CLK_AUDIOPLL2_VCO             16
> +#define IMX95_CLK_AUDIOPLL2                 17
> +#define IMX95_CLK_VIDEOPLL1_VCO             18
> +#define IMX95_CLK_VIDEOPLL1                 19
> +#define IMX95_CLK_RESERVED20                20
> +#define IMX95_CLK_RESERVED21                21
> +#define IMX95_CLK_RESERVED22                22
> +#define IMX95_CLK_RESERVED23                23
> +#define IMX95_CLK_ARMPLL_VCO                24
> +#define IMX95_CLK_ARMPLL_PFD0_UNGATED       25
> +#define IMX95_CLK_ARMPLL_PFD0               26
> +#define IMX95_CLK_ARMPLL_PFD1_UNGATED       27
> +#define IMX95_CLK_ARMPLL_PFD1               28
> +#define IMX95_CLK_ARMPLL_PFD2_UNGATED       29
> +#define IMX95_CLK_ARMPLL_PFD2               30
> +#define IMX95_CLK_ARMPLL_PFD3_UNGATED       31
> +#define IMX95_CLK_ARMPLL_PFD3               32
> +#define IMX95_CLK_DRAMPLL_VCO               33
> +#define IMX95_CLK_DRAMPLL                   34
> +#define IMX95_CLK_HSIOPLL_VCO               35
> +#define IMX95_CLK_HSIOPLL                   36
> +#define IMX95_CLK_LDBPLL_VCO                37
> +#define IMX95_CLK_LDBPLL                    38
> +#define IMX95_CLK_EXT1                      39
> +#define IMX95_CLK_EXT2                      40
> +
> +#define IMX95_CCM_NUM_CLK_SRC               41

All my comments from previous version or for other patchsets you sent
recently apply.

Best regards,
Krzysztof