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McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" Subject: [patch v2 00/30] x86/apic: Rework APIC registration Date: Tue, 23 Jan 2024 14:10:49 +0100 (CET) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: This is a breakout from: https://lore.kernel.org/all/20230807130108.853357011@linutronix.de addressing the issues of the current topology code: - Wrong core count on hybrid systems - Heuristics based size information for packages and dies which are failing to work correctly with certain command line parameters. - Full evaluation fail for a theoretical hybrid system which boots from an E-core - The complete insanity of manipulating global data from firmware parsers or the XEN/PV fake SMP enumeration. The latter is really a piece of art. This series addresses this by - Consolidating all topology relevant functionality into one place - Providing separate interfaces for boot time and ACPI hotplug operations - A sane ordering of command line options and restrictions - A sensible way to handle the BSP problem in kdump kernels instead of the unreliable command line option. - Confinement of topology relevant variables by replacing the XEN/PV SMP enumeration fake with something halfways sensible. - Evaluation of sizes by analysing the topology via the CPUID provided APIC ID segmentation and the actual APIC IDs which are registered at boot time. - Removal of heuristics and broken size calculations The idea behind this is the following: The APIC IDs describe the system topology in multiple domain levels. The CPUID topology parser provides the information which part of the APIC ID is associated to the individual levels (Intel terminology): [ROOT][PACKAGE][DIEGRP][DIE][TILE][MODULE][CORE][THREAD] The root space contains the package (socket) IDs. Not enumerated levels consume 0 bits space, but conceptually they are always represented. If e.g. only CORE and THREAD levels are enumerated then the DIEGRP, DIE, MODULE and TILE have the same physical ID as the PACKAGE. If SMT is not supported, then the THREAD domain is still used. It then has the same physical ID as the CORE domain and is the only child of the core domain. This allows an unified view on the system independent of the enumerated domain levels without requiring any conditionals in the code. AMD does only expose 4 domain levels with obviously different terminology, but that can be easily mapped into the Intel variant with a trivial lookup table added to the CPUID parser. The resulting topology information of an ADL hybrid system with 8 P-Cores and 8 E-Cores looks like this: CPU topo: Max. logical packages: 1 CPU topo: Max. logical dies: 1 CPU topo: Max. dies per package: 1 CPU topo: Max. threads per core: 2 CPU topo: Num. cores per package: 16 CPU topo: Num. threads per package: 24 CPU topo: Allowing 24 present CPUs plus 0 hotplug CPUs CPU topo: Thread : 24 CPU topo: Core : 16 CPU topo: Module : 1 CPU topo: Tile : 1 CPU topo: Die : 1 CPU topo: Package : 1 This is happening on the boot CPU before any of the APs is started and provides correct size information right from the start. Even the XEN/PV trainwreck makes use of this now. On Dom0 it utilizes the MADT and on DomU it provides fake APIC IDs, which combined with the provided CPUID information make it at least look halfways realistic instead of claiming to have one CPU per package as the current upstream code does. This is solely addressing the core topology issues, but there is a plan for further consolidation of other topology related information into one single source of information instead of having a gazillion of localized special parsers and representations all over the place. There are quite some other things which can be simplified on top of this, like updating the various cpumasks during CPU bringup, but that's all left for later. Changes vs. V1: - Breakout of the actual topology management changes - Adopt DIEGRP - Different approach to identify the BSP on enumeration (Rui) The current series applies on top of git://git.kernel.org/pub/scm/linux/kernel/git/tglx/devel.git topo-cleanup-v2 and is available from git here: git://git.kernel.org/pub/scm/linux/kernel/git/tglx/devel.git topo-full-v2 Thanks, tglx --- Documentation/admin-guide/kdump/kdump.rst | 7 Documentation/admin-guide/kernel-parameters.txt | 9 Documentation/arch/x86/topology.rst | 24 arch/x86/events/intel/cstate.c | 2 arch/x86/events/intel/uncore.c | 2 arch/x86/events/intel/uncore_nhmex.c | 4 arch/x86/events/intel/uncore_snb.c | 8 arch/x86/events/intel/uncore_snbep.c | 18 arch/x86/events/rapl.c | 2 arch/x86/include/asm/apic.h | 10 arch/x86/include/asm/cpu.h | 10 arch/x86/include/asm/mpspec.h | 2 arch/x86/include/asm/perf_event_p4.h | 4 arch/x86/include/asm/processor.h | 2 arch/x86/include/asm/smp.h | 6 arch/x86/include/asm/topology.h | 53 - arch/x86/kernel/acpi/boot.c | 59 - arch/x86/kernel/apic/apic.c | 186 --- arch/x86/kernel/cpu/Makefile | 12 arch/x86/kernel/cpu/cacheinfo.c | 2 arch/x86/kernel/cpu/common.c | 33 arch/x86/kernel/cpu/debugfs.c | 7 arch/x86/kernel/cpu/mce/inject.c | 3 arch/x86/kernel/cpu/microcode/intel.c | 2 arch/x86/kernel/cpu/topology.c | 484 ++++++++++ arch/x86/kernel/cpu/topology.h | 11 arch/x86/kernel/cpu/topology_common.c | 45 arch/x86/kernel/devicetree.c | 2 arch/x86/kernel/jailhouse.c | 2 arch/x86/kernel/mpparse.c | 17 arch/x86/kernel/process.c | 2 arch/x86/kernel/setup.c | 9 arch/x86/kernel/smpboot.c | 219 ---- arch/x86/xen/apic.c | 14 arch/x86/xen/enlighten_pv.c | 3 arch/x86/xen/smp.c | 2 arch/x86/xen/smp.h | 2 arch/x86/xen/smp_pv.c | 58 - drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 2 drivers/hwmon/coretemp.c | 2 drivers/hwmon/fam15h_power.c | 2 drivers/platform/x86/intel/uncore-frequency/uncore-frequency.c | 2 drivers/powercap/intel_rapl_common.c | 2 drivers/thermal/intel/intel_hfi.c | 2 drivers/thermal/intel/intel_powerclamp.c | 2 drivers/thermal/intel/x86_pkg_temp_thermal.c | 2 46 files changed, 698 insertions(+), 655 deletions(-)