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Date: Tue, 23 Jan 2024 07:42:00 -0800
From: "H. Peter Anvin" <hpa@zytor.com>
To: Borislav Petkov <bp@alien8.de>, Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
CC: herbert@gondor.apana.org.au, davem@davemloft.net,
        linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org,
        tglx@linutronix.de, mingo@redhat.com, dave.hansen@linux.intel.com,
        x86@kernel.org, seanjc@google.com, kim.phillips@amd.com,
        kirill.shutemov@linux.intel.com, jmattson@google.com,
        babu.moger@amd.com, kai.huang@intel.com, acme@redhat.com, aik@amd.com,
        namhyung@kernel.org, CobeChen@zhaoxin.com, TimGuo@zhaoxin.com,
        LeoLiu-oc@zhaoxin.com, GeorgeXue@zhaoxin.com
Subject: =?US-ASCII?Q?Re=3A_=5BPATCH_v2_2/3=5D_x86/cpufeatures=3A_Add_?= =?US-ASCII?Q?CPU_feature_flags_for_Zhaoxin_Hash_Engine?=
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On January 23, 2024 1:44:27 AM PST, Borislav Petkov <bp@alien8=2Ede> wrote:
>On Tue, Jan 23, 2024 at 10:28:51AM +0800, Tony W Wang-oc wrote:
>> Zhaoxin CPUs have implemented the SHA(Secure Hash Algorithm) as its
>> instrucions=2E
>> Add two CPU feature flags indicated by CPUID=2E(EAX=3DC0000001,ECX=3D0)=
:EDX
>> bit 25/26 which will be used by Zhaoxin SHA driver=2E
>>=20
>> Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin=2Ecom>
>> ---
>>  arch/x86/include/asm/cpufeatures=2Eh       | 4 +++-
>>  tools/arch/x86/include/asm/cpufeatures=2Eh | 4 +++-
>>  2 files changed, 6 insertions(+), 2 deletions(-)
>>=20
>> diff --git a/arch/x86/include/asm/cpufeatures=2Eh b/arch/x86/include/as=
m/cpufeatures=2Eh
>> index 29cb275a219d=2E=2E28b0e62dbdf5 100644
>> --- a/arch/x86/include/asm/cpufeatures=2Eh
>> +++ b/arch/x86/include/asm/cpufeatures=2Eh
>> @@ -145,7 +145,7 @@
>>  #define X86_FEATURE_RDRAND		( 4*32+30) /* RDRAND instruction */
>>  #define X86_FEATURE_HYPERVISOR		( 4*32+31) /* Running on a hypervisor =
*/
>> =20
>> -/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, wor=
d 5 */
>> +/* VIA/Cyrix/Centaur/Zhaoxin-defined CPU features, CPUID level 0xC0000=
001, word 5 */
>
>Does that mean that all those companies agree on the contents of this
>CPUID leaf?
>
>>  #define X86_FEATURE_XSTORE		( 5*32+ 2) /* "rng" RNG present (xstore) *=
/
>>  #define X86_FEATURE_XSTORE_EN		( 5*32+ 3) /* "rng_en" RNG enabled */
>>  #define X86_FEATURE_XCRYPT		( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt)=
 */
>> @@ -156,6 +156,8 @@
>>  #define X86_FEATURE_PHE_EN		( 5*32+11) /* PHE enabled */
>>  #define X86_FEATURE_PMM			( 5*32+12) /* PadLock Montgomery Multiplier =
*/
>>  #define X86_FEATURE_PMM_EN		( 5*32+13) /* PMM enabled */
>> +#define X86_FEATURE_PHE2		( 5*32+25) /* "phe2" Zhaoxin Hash Engine */
>> +#define X86_FEATURE_PHE2_EN		( 5*32+26) /* "phe2_en" PHE2 enabled */
>						      ^^^^^^^^^
>
>From: Documentation/arch/x86/cpuinfo=2Erst
>
>"a: Feature flags can be derived from the contents of CPUID leaves=2E
>------------------------------------------------------------------
>These feature definitions are organized mirroring the layout of CPUID
>leaves and grouped in words with offsets as mapped in enum cpuid_leafs
>in cpufeatures=2Eh (see arch/x86/include/asm/cpufeatures=2Eh for details)=
=2E
>If a feature is defined with a X86_FEATURE_<name> definition in
>cpufeatures=2Eh, and if it is detected at run time, the flags will be
>displayed accordingly in /proc/cpuinfo=2E For example, the flag "avx2"
>comes from X86_FEATURE_AVX2 in cpufeatures=2Eh=2E"
>
>Is your grep broken?
>

Well, Centaur bought Cyrix, and then VIA bought Centaur=2E I think Zhaoxin=
 is a joint venture between VIA and the City of Shanghai, or something like=
 that?