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Date: Tue, 23 Jan 2024 17:27:13 +0000
From: Conor Dooley <conor@kernel.org>
To: Frank Li <Frank.Li@nxp.com>
Cc: thinh.nguyen@synopsys.com, robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
	balbi@kernel.org, devicetree@vger.kernel.org,
	gregkh@linuxfoundation.org, imx@lists.linux.dev,
	linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org,
	mark.rutland@arm.com, mathias.nyman@intel.com, pku.leo@gmail.com,
	sergei.shtylyov@cogentembedded.com
Subject: Re: [PATCH 1/2] dt-bindings: usb: dwc3: Add system bus request info
Message-ID: <20240123-poking-geography-33be2b5ae578@spud>
References: <20240123170206.3702413-1-Frank.Li@nxp.com>
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On Tue, Jan 23, 2024 at 12:02:05PM -0500, Frank Li wrote:
> Add device tree binding allow platform overwrite default value of *REQIN =
in
> GSBUSCFG0.

Why might a platform actually want to do this? Why does this need to be
set at the board level and being aware of which SoC is in use is not
sufficient for the driver to set the correct values?

Thanks,
Conor.

>=20
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
>  .../devicetree/bindings/usb/snps,dwc3.yaml    | 36 +++++++++++++++++++
>  1 file changed, 36 insertions(+)
>=20
> diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Docum=
entation/devicetree/bindings/usb/snps,dwc3.yaml
> index 8f5d250070c78..43e7fea3f6798 100644
> --- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
> +++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
> @@ -439,6 +439,42 @@ properties:
>      items:
>        enum: [1, 4, 8, 16, 32, 64, 128, 256]
> =20
> +  snps,des-wr-reqinfo:
> +    description: Value for DESEWRREQIN of GSBUSCFG0 register.
> +      ----------------------------------------------------------------
> +       MBUS_TYPE| bit[3]       |bit[2]       |bit[1]     |bit[0]
> +      ----------------------------------------------------------------
> +       AHB      |Cacheable     |Bufferable   |Privilegge |Data
> +       AXI3     |Write Allocate|Read Allocate|Cacheable  |Bufferable
> +       AXI4     |Allocate Other|Allocate     |Modifiable |Bufferable
> +       AXI4     |Other Allocate|Allocate     |Modifiable |Bufferable
> +       Native   |Same as AXI   |Same as AXI  |Same as AXI|Same as AXI
> +      ----------------------------------------------------------------
> +      The AHB, AXI3, AXI4, and PCIe busses use different names for certa=
in
> +      signals, which have the same meaning:
> +      Bufferable =3D Posted
> +      Cacheable =3D Modifiable =3D Snoop (negation of No Snoop)
> +    $ref: /schemas/types.yaml#/definitions/uint8
> +    maxItem: 15
> +
> +  snps,des-rd-reqinfo:
> +    description: Value for DESRDREQIN of GSBUSCFG0 register. ref
> +      snps,des-wr-reqinfo
> +    $ref: /schemas/types.yaml#/definitions/uint8
> +    maxItem: 15
> +
> +  snps,dat-wr-reqinfo:
> +    description: Value for DATWRREQIN of GSBUSCFG0 register. ref
> +      snps,des-wr-reqinfo
> +    $ref: /schemas/types.yaml#/definitions/uint8
> +    maxItem: 15
> +
> +  snps,des-wr-reqinfo:
> +    description: Value for DATWRREQIN of GSBUSCFG0 register. ref
> +      snps,des-wr-reqinfo
> +    $ref: /schemas/types.yaml#/definitions/uint8
> +    maxItem: 15
> +
>    num-hc-interrupters:
>      maximum: 8
>      default: 1
> --=20
> 2.34.1
>=20

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