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From: Xaver Hugl <xaver.hugl@gmail.com>
Date: Tue, 23 Jan 2024 19:02:19 +0100
Message-ID: <CAFZQkGyf5MxKeGgz09kgyYTp+g-Jk2uaiQkmzSX7BDGHpcz0CQ@mail.gmail.com>
Subject: Re: [PATCH v2 2/2] drm/amdgpu: Implement check_async_props for planes
To: Harry Wentland <harry.wentland@amd.com>
Cc: =?UTF-8?B?VmlsbGUgU3lyasOkbMOk?= <ville.syrjala@linux.intel.com>, 
	=?UTF-8?Q?Andr=C3=A9_Almeida?= <andrealmeid@igalia.com>, daniel@ffwll.ch, 
	=?UTF-8?B?TWFyZWsgT2zFocOhaw==?= <maraeo@gmail.com>, 
	=?UTF-8?Q?Michel_D=C3=A4nzer?= <michel.daenzer@mailbox.org>, 
	linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org, 
	Pekka Paalanen <ppaalanen@gmail.com>, dri-devel@lists.freedesktop.org, 
	kernel-dev@igalia.com, alexander.deucher@amd.com, 
	Dave Airlie <airlied@gmail.com>, christian.koenig@amd.com, 
	Joshua Ashton <joshua@froggi.es>
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Am Mo., 22. Jan. 2024 um 16:50 Uhr schrieb Harry Wentland
<harry.wentland@amd.com>:
>
>
>
> On 2024-01-19 13:25, Ville Syrj=C3=A4l=C3=A4 wrote:
> > On Fri, Jan 19, 2024 at 03:12:35PM -0300, Andr=C3=A9 Almeida wrote:
> >> AMD GPUs can do async flips with changes on more properties than just
> >> the FB ID, so implement a custom check_async_props for AMD planes.
> >>
> >> Allow amdgpu to do async flips with IN_FENCE_ID and FB_DAMAGE_CLIPS
> >> properties. For userspace to check if a driver support this two
> >> properties, the strategy for now is to use TEST_ONLY commits.
> >>
> >> Signed-off-by: Andr=C3=A9 Almeida <andrealmeid@igalia.com>
> >> ---
> >> v2: Drop overlay plane option for now
> >>
> >>   .../amd/display/amdgpu_dm/amdgpu_dm_plane.c   | 29 +++++++++++++++++=
++
> >>   1 file changed, 29 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b=
/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
> >> index 116121e647ca..7afe8c1b62d4 100644
> >> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
> >> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
> >> @@ -25,6 +25,7 @@
> >>    */
> >>
> >>   #include <drm/drm_atomic_helper.h>
> >> +#include <drm/drm_atomic_uapi.h>
> >>   #include <drm/drm_blend.h>
> >>   #include <drm/drm_gem_atomic_helper.h>
> >>   #include <drm/drm_plane_helper.h>
> >> @@ -1430,6 +1431,33 @@ static void amdgpu_dm_plane_drm_plane_destroy_s=
tate(struct drm_plane *plane,
> >>      drm_atomic_helper_plane_destroy_state(plane, state);
> >>   }
> >>
> >> +static int amdgpu_dm_plane_check_async_props(struct drm_property *pro=
p,
> >> +                                      struct drm_plane *plane,
> >> +                                      struct drm_plane_state *plane_s=
tate,
> >> +                                      struct drm_mode_object *obj,
> >> +                                      u64 prop_value, u64 old_val)
> >> +{
> >> +    struct drm_mode_config *config =3D &plane->dev->mode_config;
> >> +    int ret;
> >> +
> >> +    if (prop !=3D config->prop_fb_id &&
> >> +        prop !=3D config->prop_in_fence_fd &&
> >
> > IN_FENCE should just be allowed always.
> >
> >> +        prop !=3D config->prop_fb_damage_clips) {
> >
> > This seems a bit dubious to me. How is amdgpu using the damage
> > information during async flips?
>
> Yeah, I'm also not sure this is right. Has anyone tested this
> with a PSR SU panel?
>
> Harry

I attempted to, but according to
/sys/kernel/debug/dri/1/eDP-1/psr_state, PSR never kicks in on my
laptop at all. The only reason I wanted this property though is to
reduce the number of special cases for async pageflips compositors
have to implement; as it's not necessary for any functionality I think
it's also fine to leave it out.

> >> +            ret =3D drm_atomic_plane_get_property(plane, plane_state,
> >> +                                                prop, &old_val);
> >> +            return drm_atomic_check_prop_changes(ret, old_val, prop_v=
alue, prop);
> >> +    }
> >> +
> >> +    if (plane_state->plane->type !=3D DRM_PLANE_TYPE_PRIMARY) {
> >> +            drm_dbg_atomic(prop->dev,
> >> +                           "[OBJECT:%d] Only primary planes can be ch=
anged during async flip\n",
> >> +                           obj->id);
> >> +            return -EINVAL;
> >> +    }
> >> +
> >> +    return 0;
> >> +}
> >> +
> >>   static const struct drm_plane_funcs dm_plane_funcs =3D {
> >>      .update_plane   =3D drm_atomic_helper_update_plane,
> >>      .disable_plane  =3D drm_atomic_helper_disable_plane,
> >> @@ -1438,6 +1466,7 @@ static const struct drm_plane_funcs dm_plane_fun=
cs =3D {
> >>      .atomic_duplicate_state =3D amdgpu_dm_plane_drm_plane_duplicate_s=
tate,
> >>      .atomic_destroy_state =3D amdgpu_dm_plane_drm_plane_destroy_state=
,
> >>      .format_mod_supported =3D amdgpu_dm_plane_format_mod_supported,
> >> +    .check_async_props =3D amdgpu_dm_plane_check_async_props,
> >>   };
> >>
> >>   int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
> >> --
> >> 2.43.0
> >