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Date: Wed, 24 Jan 2024 00:19:21 -0800
From: Dennis Zhou <dennis@kernel.org>
To: yunhui cui <cuiyunhui@bytedance.com>,
	Alexandre Ghiti <alexghiti@rivosinc.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Geert Uytterhoeven <geert@linux-m68k.org>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [External] [PATCH] riscv: Fix wrong size passed to
 local_flush_tlb_range_asid()
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References: <20240123132730.2297719-1-alexghiti@rivosinc.com>
 <CAEEQ3wk5edUFTuE3H3KDGkCXj0+=i7Z1BM2M+6X-Tk9_m8X_iQ@mail.gmail.com>
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Hello,

On Wed, Jan 24, 2024 at 10:44:12AM +0800, yunhui cui wrote:
> Hi Alexandre,
> 
> On Tue, Jan 23, 2024 at 9:31 PM Alexandre Ghiti <alexghiti@rivosinc.com> wrote:
> >
> > local_flush_tlb_range_asid() takes the size as argument, not the end of
> > the range to flush, so fix this by computing the size from the end and
> > the start of the range.
> >
> > Fixes: 7a92fc8b4d20 ("mm: Introduce flush_cache_vmap_early()")
> > Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> > ---
> >  arch/riscv/mm/tlbflush.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
> > index 8d12b26f5ac3..9619965f6501 100644
> > --- a/arch/riscv/mm/tlbflush.c
> > +++ b/arch/riscv/mm/tlbflush.c
> > @@ -68,7 +68,7 @@ static inline void local_flush_tlb_range_asid(unsigned long start,
> >
> >  void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
> >  {
> > -       local_flush_tlb_range_asid(start, end, PAGE_SIZE, FLUSH_TLB_NO_ASID);
> > +       local_flush_tlb_range_asid(start, end - start, PAGE_SIZE, FLUSH_TLB_NO_ASID);
> >  }
> 

Well this was a miss during code review.. I'm going to take another look
tomorrow and then likely pull this into a fixes branch.

> What makes me curious is that this patch has not been tested?
> BTW, It is best to keep the parameter order of all functions in
> tlbflush.c consistent: cpumask, start, size, stride, asid.
> 

I can't speak to the riscv communities testing/regression suites, but
this would only be caught in a performance regression test.

That being said, Alexandre, can you please lmk what level of testing
this has gone through?

Thanks,
Dennis