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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Wed, Jan 03, 2024 at 02:50:04PM +0100, Konrad Dybcio wrote: > On 20.12.2023 09:30, Manivannan Sadhasivam wrote: > > On Wed, Dec 20, 2023 at 01:35:27AM +0100, Konrad Dybcio wrote: > >> On 18.12.2023 13:07, Manivannan Sadhasivam wrote: > >>> QMP PHY used in SC8280XP requires 3 clocks: > >>> > >>> * ref - 19.2MHz reference clock from RPMh > >>> * ref_aux - Auxiliary reference clock from GCC > >>> * qref - QREF clock from GCC > >>> > >>> Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") > >>> Signed-off-by: Manivannan Sadhasivam > >>> --- > >>> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 18 ++++++++++++------ > >>> 1 file changed, 12 insertions(+), 6 deletions(-) > >>> > >>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > >>> index cad59af7ccef..37344abbe8bf 100644 > >>> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > >>> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi > >>> @@ -2256,9 +2256,12 @@ ufs_mem_phy: phy@1d87000 { > >>> compatible = "qcom,sc8280xp-qmp-ufs-phy"; > >>> reg = <0 0x01d87000 0 0x1000>; > >>> > >>> - clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>, > >>> - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; > >>> - clock-names = "ref", "ref_aux"; > >>> + clocks = <&rpmhcc RPMH_CXO_CLK>, > >>> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, > >>> + <&gcc GCC_UFS_CARD_CLKREF_CLK>; > >> GCC_UFS_REF_CLKREF_CLK > > > > I'm not sure about this CLK. So I kept it as it is until I verify it. > I am quite sure everything *UFS_CARD_* refers to the other UFS host.. > We cannot infer that from the naming. There is a chance that the same clock could be routed to MEM_PHY internally. Moreover, there is no separate "ref" clock for MEM_PHY though. - Mani -- மணிவண்ணன் சதாசிவம்