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Wed, 24 Jan 2024 02:02:39 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240122225710.1952066-1-peter.griffin@linaro.org> <20240122225710.1952066-3-peter.griffin@linaro.org> In-Reply-To: From: Peter Griffin Date: Wed, 24 Jan 2024 10:02:27 +0000 Message-ID: Subject: Re: [PATCH 2/9] soc: samsung: exynos-pmu: Add exynos_pmu_update/read/write APIs and SoC quirks To: Sam Protsenko Cc: arnd@arndb.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux@roeck-us.net, wim@linux-watchdog.org, conor+dt@kernel.org, alim.akhtar@samsung.com, jaewon02.kim@samsung.com, chanho61.park@samsung.com, kernel-team@android.com, tudor.ambarus@linaro.org, andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, linux-fsd@tesla.com, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Sam, Thanks for the review feedback. On Tue, 23 Jan 2024 at 18:56, Sam Protsenko wr= ote: > > On Mon, Jan 22, 2024 at 4:57=E2=80=AFPM Peter Griffin wrote: > > > > Newer Exynos SoCs have atomic set/clear bit hardware for PMU registers = as > > these registers can be accessed by multiple masters. Some platforms als= o > > protect the PMU registers for security hardening reasons so they can't = be > > written by normal world and are only write acessible in el3 via a SMC c= all. > > > > Add support for both of these usecases using SoC specific quirks that a= re > > determined from the DT compatible string. > > > > Drivers which need to read and write PMU registers should now use these > > new exynos_pmu_*() APIs instead of obtaining a regmap using > > syscon_regmap_lookup_by_phandle() > > > > Depending on the SoC specific quirks, the exynos_pmu_*() APIs will acce= ss > > the PMU register in the appropriate way. > > > > Signed-off-by: Peter Griffin > > --- > > drivers/soc/samsung/exynos-pmu.c | 209 ++++++++++++++++++++++++- > > drivers/soc/samsung/exynos-pmu.h | 4 + > > include/linux/soc/samsung/exynos-pmu.h | 28 ++++ > > 3 files changed, 234 insertions(+), 7 deletions(-) > > > > [snip] > > > + > > +int exynos_pmu_update_bits(unsigned int offset, unsigned int mask, > > + unsigned int val) > > +{ > > + if (pmu_context->pmu_data && > > + pmu_context->pmu_data->quirks & QUIRK_PMU_ALIVE_WRITE_SEC) > > + return rmw_priv_reg(pmu_context->pmu_base_pa + offset, > > + mask, val); > > + > > + return regmap_update_bits(pmu_context->pmureg, offset, mask, va= l); > > +} > > +EXPORT_SYMBOL(exynos_pmu_update_bits); > > + > > This seems a bit hacky, from the design perspective. This way the user > will have to worry about things like driver dependencies, making sure > everything is instantiated in a correct order, etc. It also hides the > details otherwise visible through "syscon-phandle" property in the > device tree. In v2 I will keep the phandle to pmu_system_controller in DT, and add some -EPROBE_DEFER logic (See my email with Krzysztof). > Can we instead rework it by overriding regmap > implementation for Exynos specifics, and then continue to use it in > the leaf drivers via "syscon-phandle" property? I did look at that possibility first, as like you say it would avoid updating the leaf drivers to use the new API. Unfortunately a SMC backend to regmap was already tried and nacked upstream pretty hard. See here https://lore.kernel.org/lkml/20210723163759.GI5221@sirena.org.uk/T= / regards, Peter.