Received-SPF: pass (google.com: domain of linux-kernel+bounces-37301-linux.lists.archive=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99;
Message-ID: <4e495bd7449159b9fe1710b673b6f9b4f185862d.camel@pengutronix.de>
Subject: Re: [PATCH 2/2] drm/etnaviv: Disable SH_EU clock gating on
 VIPNano-Si+
From: Lucas Stach <l.stach@pengutronix.de>
To: Philipp Zabel <p.zabel@pengutronix.de>, Russell King
 <linux+etnaviv@armlinux.org.uk>, Christian Gmeiner
 <christian.gmeiner@gmail.com>,  David Airlie <airlied@gmail.com>, Daniel
 Vetter <daniel@ffwll.ch>
Cc: etnaviv@lists.freedesktop.org, dri-devel@lists.freedesktop.org, 
	linux-kernel@vger.kernel.org
Date: Wed, 24 Jan 2024 17:07:55 +0100
In-Reply-To: <20240124-etnaviv-npu-v1-2-a5aaf64aec65@pengutronix.de>
References: <20240124-etnaviv-npu-v1-0-a5aaf64aec65@pengutronix.de>
	 <20240124-etnaviv-npu-v1-2-a5aaf64aec65@pengutronix.de>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
User-Agent: Evolution 3.48.4 (3.48.4-1.fc38) 
Precedence: bulk
MIME-Version: 1.0

Am Mittwoch, dem 24.01.2024 um 10:22 +0100 schrieb Philipp Zabel:
> Disable SH_EU clock gating for the VIPNano-Si+ NPU on i.MX8MP.
> Taken from linux-imx lf-6.1.36-2.1.0, specifically [1].
>=20
> [1] https://github.com/nxp-imx/linux-imx/blob/lf-6.1.36-2.1.0/drivers/mxc=
/gpu-viv/hal/kernel/arch/gc_hal_kernel_hardware.c#L2747-L2761
>=20
> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
> ---
>  drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 4 ++++
>  1 file changed, 4 insertions(+)
>=20
> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etna=
viv/etnaviv_gpu.c
> index 9b8445d2a128..e28332a2560d 100644
> --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> @@ -641,6 +641,10 @@ static void etnaviv_gpu_enable_mlcg(struct etnaviv_g=
pu *gpu)
>  		pmc |=3D VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE |
>  		       VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA;
> =20
> +	/* Disable SH_EU clock gating on affected core revisions. */
> +	if (etnaviv_is_model_rev(gpu, GC8000, 0x8002))
> +		pmc |=3D VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH_EU;
> +
With the other clock gate disables in the driver we match on all chip
revisions found in downstream drivers, even if etnaviv hasn't been
tested with the specific GPU. To stay consistent, this workaround
should also match GC8000r7200 and GC9200r6304, same as the downstream
driver.

Regards,
Lucas