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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1706116131; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=romx/hMVnXU+YClTIP+lZWzqpiWykqr15lDUZgoS4EA=; b=QNHpXucdZFKUH+WLTfvF90rOkNfXLjgudSf0YujzPsNFqCRFdlnOYITnw7FwgwAzwfnany rJru6oMuuk7LQtuIrcycjfXUIiqErr899+3mJ6PDDFXwWT7N26SvMeHBUoNVkLBV2w1lrW 3WZ5A/bfMUJd9lwObX33vRQyZ84IEvXiRRV7/83OzO2bSyzqpK/p4GWoVXUClVqQ7zZmKt xt3cCvp0FDTFpz21scmoOfYenTt5hC3Ly8DM6S/x9Qo6qYtE1UpcqBT/DEspq+eAcI/Our UV9WFuL5o0WcLX0zay0GZQMecgpFxnppXok1ahg4uf32zTf4xdSXK60hh04jPg== Date: Wed, 24 Jan 2024 18:08:48 +0100 From: Miquel Raynal To: Ezra Buehler Cc: Chuanhong Guo , linux-mtd@lists.infradead.org, Richard Weinberger , Vignesh Raghavendra , Patrice Chotard , Boris Brezillon , Christophe Kerello , Mark Brown , Daniel Palmer , open list , quic_sridsn@quicinc.com, quic_mdalam@quicinc.com Subject: Re: [PATCH v2] mtd: spinand: add support for ESMT F50x1G41LB Message-ID: <20240124180848.3647d5c9@xps-13> In-Reply-To: References: <20220413083824.247136-1-gch981213@gmail.com> <20220413145843.46a3d9b5@xps13> Organization: Bootlin X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.33; x86_64-pc-linux-gnu) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: miquel.raynal@bootlin.com Hi Ezra, ezra@easyb.ch wrote on Tue, 23 Jan 2024 19:54:06 +0200: > Hi Chuanhong Guo, >=20 > On Wed, 13 Apr 2022 22:50:43 +0800 Chuanhong Guo wr= ote: > > Their device ID aren't conflicting yet, so nothing will happen > > at the moment. =20 >=20 > Since commit aa08bf187f32 ("mtd: spinand: esmt: add support for > F50D2G41KA") we have a conflict with the GigaDevice GD5F1GQ5UExxG > (manufacturer ID 0xC8, device ID 0x51), preventing our board from > booting. >=20 > > There is a solution for future conflict: Recent SPI-NAND chips > > contain a parameter page which has the exact chip vendor > > and model. We can do one more detection with the parameter > > page content. > > Winbond W25N01KV is a 2k+96 SPI-NAND with 4-bit ECC. > > It uses the exact same chip id as the current W25N01GV > > (2k+64 1-bit ECC). We need to support detection using > > parameter page for this crazy decision by Winbond anyway. > > I'll try to code something for this with my free time. > > > > My current idea is: We first do a detection based on chip id. > > If that failed, try to read the parameter page. If we got a > > valid one, match the chip vendor and model string. =20 >=20 > According to the datasheets, the ESMT chips actually have a 5 byte ID, > the last 3 bytes being 0x7F (JEDEC Maker Code Continuation Code). Why > can't we simply extend the ID in esmt.c (as you had it in your original > patch) and increase SPINAND_MAX_ID_LEN to 5? Or, alternatively, only > extend the ID to 4 bytes? >=20 > If that is the way to go, I would be happy to provide the patches. Please send the patches. Chuanhong can you test them? Thanks, Miqu=C3=A8l