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Date: Wed, 24 Jan 2024 18:31:39 +0100
Message-Id: <CYN46F005M23.1Z11SN0VZF777@bootlin.com>
Cc: "Gregory CLEMENT" <gregory.clement@bootlin.com>, "Michael Turquette"
 <mturquette@baylibre.com>, "Stephen Boyd" <sboyd@kernel.org>, "Krzysztof
 Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, "Conor Dooley"
 <conor+dt@kernel.org>, "Thomas Bogendoerfer" <tsbogend@alpha.franken.de>,
 "Linus Walleij" <linus.walleij@linaro.org>,
 =?utf-8?q?Rafa=C5=82_Mi=C5=82ecki?= <rafal@milecki.pl>, "Philipp Zabel"
 <p.zabel@pengutronix.de>, "Vladimir Kondratiev"
 <vladimir.kondratiev@mobileye.com>, <linux-mips@vger.kernel.org>,
 <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
 <linux-kernel@vger.kernel.org>, "Thomas Petazzoni"
 <thomas.petazzoni@bootlin.com>, "Tawfik Bayouk"
 <tawfik.bayouk@mobileye.com>, <linux-gpio@vger.kernel.org>
To: "Rob Herring" <robh@kernel.org>
From: =?utf-8?q?Th=C3=A9o_Lebrun?= <theo.lebrun@bootlin.com>
Subject: Re: [PATCH v3 10/17] pinctrl: eyeq5: add platform driver
References: <20240123-mbly-clk-v3-0-392b010b8281@bootlin.com>
 <20240123-mbly-clk-v3-10-392b010b8281@bootlin.com>
 <20240124151949.GB930997-robh@kernel.org>
In-Reply-To: <20240124151949.GB930997-robh@kernel.org>

Hello,

On Wed Jan 24, 2024 at 4:19 PM CET, Rob Herring wrote:
> On Tue, Jan 23, 2024 at 07:46:55PM +0100, Th=C3=A9o Lebrun wrote:
> > Add the Mobileye EyeQ5 pin controller driver. It might grow to add late=
r
> > support of other platforms from Mobileye. It belongs to a syscon region
> > called OLB.
> >=20
> > Existing pins and their function live statically in the driver code
> > rather than in the devicetree, see compatible match data.
> >
> > Signed-off-by: Th=C3=A9o Lebrun <theo.lebrun@bootlin.com>
> > ---

[...]

> > diff --git a/drivers/pinctrl/pinctrl-eyeq5.c b/drivers/pinctrl/pinctrl-=
eyeq5.c

[...]

> > +static const struct eq5p_match eq5p_match_a =3D {
> > +	.regs =3D {
> > +		[EQ5P_PD] =3D 0x0C0,
> > +		[EQ5P_PU] =3D 0x0C4,
> > +		[EQ5P_DS_LOW] =3D 0x0D0,
> > +		[EQ5P_DS_HIGH] =3D 0x0D4,
> > +		[EQ5P_IOCR] =3D 0x0B0,
> > +	},
> > +	.pins =3D eq5p_pins_a,
> > +	.npins =3D ARRAY_SIZE(eq5p_pins_a),
> > +	.funcs =3D eq5p_functions_a,
> > +	.nfuncs =3D ARRAY_SIZE(eq5p_functions_a),
> > +};
> > +
> > +static const struct eq5p_match eq5p_match_b =3D {
> > +	.regs =3D {
> > +		[EQ5P_PD] =3D 0x0C8,
> > +		[EQ5P_PU] =3D 0x0CC,
> > +		[EQ5P_DS_LOW] =3D 0x0D8,
> > +		[EQ5P_DS_HIGH] =3D 0x0DC,
> > +		[EQ5P_IOCR] =3D 0x0B4,
> > +	},
>
> These are all the same relative offsets, so you really only need to=20
> store the base offset.

Indeed, and I don't think I had even noticed. Thanks.

> The use of 2 compatibles is a bit questionable as the programming model=
=20
> appears to be the same and only which pins differ. Surely there are=20
> some other pinctrl drivers handling mutiple instances.

I can confirm the programming model is the same across both banks. I've
addressed your comment in my answer to yours on [PATCH v3 04/17].


Thanks,

--
Th=C3=A9o Lebrun, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com