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From: Sam Protsenko <semen.protsenko@linaro.org>
Date: Wed, 24 Jan 2024 13:51:21 -0600
Message-ID: <CAPLW+4=z9cgVZgY_a6d69sGfDaErsYSc9tL8mtYdoBeahZGJyA@mail.gmail.com>
Subject: Re: [PATCH 5/7] spi: s3c64xx: Add Exynos850 support
To: Tudor Ambarus <tudor.ambarus@linaro.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Andi Shyti <andi.shyti@kernel.org>, 
	Mark Brown <broonie@kernel.org>, Rob Herring <robh+dt@kernel.org>, 
	Conor Dooley <conor+dt@kernel.org>, Alim Akhtar <alim.akhtar@samsung.com>, 
	Sylwester Nawrocki <s.nawrocki@samsung.com>, Tomasz Figa <tomasz.figa@gmail.com>, 
	Chanwoo Choi <cw00.choi@samsung.com>, linux-spi@vger.kernel.org, 
	linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, 
	linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, 
	linux-clk@vger.kernel.org
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On Wed, Jan 24, 2024 at 12:49=E2=80=AFAM Tudor Ambarus <tudor.ambarus@linar=
o.org> wrote:
>
>
>
> On 1/20/24 01:29, Sam Protsenko wrote:
> > Add SPI port configuration for Exynos850 SoC. It has 3 USI blocks which
> > can be configured in SPI mode:
> >
> >   * spi_0: BLK_PERI_SPI_0 (0x13940000)
> >   * spi_1: BLK_ALIVE_USI_CMGP00 (0x11d00000)
> >   * spi_2: BLK_ALIVE_USI_CMGP01 (0x11d20000)
> >
> > SPI FIFO depth is 64 bytes for all those SPI blocks, so the
> > .fifo_lvl_mask value is set to 0x7f. All blocks have DIV_4 as the
> > default internal clock divider, and an internal loopback mode to run
> > a loopback test.
> >
> > Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
>
> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
>
> > ---
> >  drivers/spi/spi-s3c64xx.c | 14 ++++++++++++++
> >  1 file changed, 14 insertions(+)
> >
> > diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
> > index 0e48ffd499b9..f7d623ad6ac3 100644
> > --- a/drivers/spi/spi-s3c64xx.c
> > +++ b/drivers/spi/spi-s3c64xx.c
> > @@ -1461,6 +1461,17 @@ static const struct s3c64xx_spi_port_config exyn=
os5433_spi_port_config =3D {
> >       .quirks         =3D S3C64XX_SPI_QUIRK_CS_AUTO,
> >  };
> >
> > +static const struct s3c64xx_spi_port_config exynos850_spi_port_config =
=3D {
> > +     .fifo_lvl_mask  =3D { 0x7f, 0x7f, 0x7f },
>
> I'll come with a follow up patch on top of this. Having the dt alias
> used as an index in the fifo_lvl_mask to determine the FIFO depth is
> wrong. Not only because of the dependency on the alias, but also because
> the fifo_lvl_mask value does not reflect the FIFO level reg field.
> Playing with what we have now is ok by me, I find the patch good.
>

Yeah, we just have to make sure all our patches are taken in the
correct order, to avoid any possible conflicts.

> > +     .rx_lvl_offset  =3D 15,
> > +     .tx_st_done     =3D 25,
> > +     .clk_div        =3D 4,
> > +     .high_speed     =3D true,
> > +     .clk_from_cmu   =3D true,
> > +     .has_loopback   =3D true,
> > +     .quirks         =3D S3C64XX_SPI_QUIRK_CS_AUTO,
> > +};
> > +
> >  static const struct s3c64xx_spi_port_config exynosautov9_spi_port_conf=
ig =3D {
> >       .fifo_lvl_mask  =3D { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff=
, 0x7f,
> >                           0x7f, 0x7f, 0x7f, 0x7f},
> > @@ -1515,6 +1526,9 @@ static const struct of_device_id s3c64xx_spi_dt_m=
atch[] =3D {
> >       { .compatible =3D "samsung,exynos5433-spi",
> >                       .data =3D (void *)&exynos5433_spi_port_config,
> >       },
> > +     { .compatible =3D "samsung,exynos850-spi",
> > +                     .data =3D (void *)&exynos850_spi_port_config,
> > +     },
> >       { .compatible =3D "samsung,exynosautov9-spi",
> >                       .data =3D (void *)&exynosautov9_spi_port_config,
> >       },