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Date: Thu, 25 Jan 2024 10:20:58 +0100
From: Miquel Raynal <miquel.raynal@bootlin.com>
To: William Zhang <william.zhang@broadcom.com>
Cc: Florian Fainelli <florian.fainelli@broadcom.com>, David Regan
 <dregan@broadcom.com>, dregan@mail.com, richard@nod.at, vigneshr@ti.com,
 robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
 computersforpeace@gmail.com, kdasu.kdev@gmail.com,
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 linux-kernel@vger.kernel.org, joel.peshkin@broadcom.com,
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 bcm-kernel-feedback-list@broadcom.com, andre.przywara@arm.com,
 baruch@tkos.co.il, linux-arm-kernel@lists.infradead.org,
 dan.carpenter@linaro.org
Subject: Re: [PATCH v3 02/10] ARM: dts: broadcom: bcmbca: Add NAND
 controller node
Message-ID: <20240125102058.5ae46d8a@xps-13>
In-Reply-To: <722d6bdf-9a43-436d-a9e2-4c21e1deb8c3@broadcom.com>
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	<2c10a764-f74f-45b2-8bba-77c40468f4b5@broadcom.com>
	<85c97d00-a973-46c6-974c-3dfa587ae873@broadcom.com>
	<722d6bdf-9a43-436d-a9e2-4c21e1deb8c3@broadcom.com>
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Hi William,

> >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 nand_controller: nand-co=
ntroller@1800 {
> >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =
#address-cells =3D <1>;
> >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =
#size-cells =3D <0>;
> >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =
compatible =3D "brcm,nand-bcm63138", >>>> "brcm,brcmnand-v7.1", "brcm,brcmn=
and";
> >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =
reg =3D <0x1800 0x600>, <0x2000 0x10>;
> >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =
reg-names =3D "nand", "nand-int-base";
> >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =
brcm,nand-use-wp =3D <0>;
> >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =
status =3D "disabled";
> >>>> +
> >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =
nandcs: nand@0 {
> >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0 compatible =3D "brcm,nandcs";
> >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0 reg =3D <0>;
> >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0 nand-on-flash-bbt;
> >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0 brcm,nand-ecc-use-strap; =20
> >>>
> >>> Describing the NAND chip in a SoC DTSI does not look relevant to me.
> >>> Even more if you add something like this nand-ecc-use-strap setting
> >>> which is very board dependent.
> >>> =20
> >> I am not sure if I understand you comments correctly but are you >> su=
ggesting to put this whole nand controller node into each board dts? >> We =
have other ip block nodes like SPI, uart in this same soc dtsi file >> too.=
=C2=A0 For all the bcmbca soc dtsi I am updating here(and its board >> desi=
gn), we always use the strap to for ecc setting.=C2=A0 So I thought it >> s=
hould be okay to put brcm,nand-ecc-use-strap in the default dtsi >> file. F=
or any board that uses the raw nand nand-ecc property, the >> board dts can=
 do so and override the brcm,nand-ecc-use-strap setting. =20
> >=20
> > I read Miquel's comment as meaning that the nandcs aka the NAND > chip/=
flash part description should be in the board .dts file, while the > contro=
ller itself can remain in the .dtsi file with its status =3D > "disabled" p=
roperty.
> >=20
> > Are there customer boards, that is non reference boards that might chos=
e > a different chip select number and/or not use the strap settings? =20
> In BCMBCA SoC, there is only one cs and customer design also have to use =
strap for the bootrom to boot up properly.  They can override it with dts i=
n linux but I don't think any customer would do that.
>=20
> Maybe the nand-on-flash-bbt could be possible item that customer may have=
 to set it differently if they don't follow our reference software design.
>=20
> I will move the nand-on-flash-bbt to the board dts but I would like to ke=
ep the other default nandcs settings in SoC.dsti if that is not too out of =
the conventional rule and Miquel is okay with it.

I think there is a global misunderstanding regarding the use of the
nand-ecc-* properties. These are not the default. The default is the OS
choice and depends on the NAND capabilities. The OS will always try to
match the closest ECC settings offered by the engine, based on the NAND
chip requirements which are discoverable. If you want to maximize your
strength, it is also possible to tell the OS with a dedicated (generic)
property. And only if you want something different, you may use these
properties, but they should be the exception rather than the rule.

Overriding this with a strap is a bad hardware design on commercial
products IMO. I am totally fine with the idea of a strap to choose
the ECC configuration for development boards/evaluation kits, but once
you've decided which setting you want you cannot change it for the
lifetime of your project (or with a lot of difficulties) so I don't see
the point of such a strap. So really, I don't like the idea of defining
by default a variable which asks for an override of the defaults, even
though many of your customers might want to use that.

So, anything that is design dependent (the chip CS, ECC
configuration, etc) should go into the board DTS, and what is SoC
related hardware (like the definition of the NAND controller) should
stay in the DTSI, as properly clarified by Florian.

Thanks,
Miqu=C3=A8l