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Thu, 25 Jan 2024 01:28:03 -0800 (PST) Received: from [127.0.1.1] ([79.115.23.25]) by smtp.gmail.com with ESMTPSA id f19-20020a056402005300b00554af5ec62asm17356391edu.8.2024.01.25.01.28.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 01:28:02 -0800 (PST) From: Abel Vesa Date: Thu, 25 Jan 2024 11:27:45 +0200 Subject: [PATCH 1/5] dt-bindings: clock: sm8550-dispcc: Drop the Disp AHB clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20240125-dispcc-sm8550-sm8650-drop-disp-ahb-clk-v1-1-0f8d96156156@linaro.org> References: <20240125-dispcc-sm8550-sm8650-drop-disp-ahb-clk-v1-0-0f8d96156156@linaro.org> In-Reply-To: <20240125-dispcc-sm8550-sm8650-drop-disp-ahb-clk-v1-0-0f8d96156156@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong Cc: Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE The Disp AHB clock is not registered, but enabled on probe, by the SM8650 and SM8550 GCC drivers. So drop the clock from dispcc node. Fixes: 553f9bd45554 ("dt-bindings: clock: document SM8550 DISPCC clock controller") Signed-off-by: Abel Vesa --- Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml index c129f8c16b50..6660d38bef86 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml @@ -25,7 +25,6 @@ properties: items: - description: Board XO source - description: Board Always On XO source - - description: Display's AHB clock - description: sleep clock - description: Byte clock from DSI PHY0 - description: Pixel clock from DSI PHY0 @@ -82,7 +81,6 @@ examples: reg = <0x0af00000 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, - <&gcc GCC_DISP_AHB_CLK>, <&sleep_clk>, <&dsi0_phy 0>, <&dsi0_phy 1>, -- 2.34.1