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Thu, 25 Jan 2024 10:24:50 GMT Received: from hu-lxu5-sha.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 25 Jan 2024 02:24:45 -0800 From: Ling Xu To: , , , , CC: , , , , , , Ling Xu Subject: [PATCH 2/2] arm64: dts: qcom: sm8650: Add dma-coherent property Date: Thu, 25 Jan 2024 15:54:13 +0530 Message-ID: <20240125102413.3016-3-quic_lxu5@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240125102413.3016-1-quic_lxu5@quicinc.com> References: <20240125102413.3016-1-quic_lxu5@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 4cPmhKFStnImBHmysedTbz1PTCUTylIU X-Proofpoint-ORIG-GUID: 4cPmhKFStnImBHmysedTbz1PTCUTylIU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-25_05,2024-01-25_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 suspectscore=0 mlxscore=0 mlxlogscore=622 adultscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 impostorscore=0 spamscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401190000 definitions=main-2401250070 Add dma-coherent property to fastRPC context bank nodes to pass dma sequence test in fastrpc sanity test, ensure that data integrity is maintained during DMA operations. Signed-off-by: Ling Xu --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 2df77123a8c7..ed0d0ca34fd4 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -4808,6 +4808,7 @@ iommus = <&apps_smmu 0x1003 0x80>, <&apps_smmu 0x1043 0x20>; + dma-coherent; }; compute-cb@4 { @@ -4816,6 +4817,7 @@ iommus = <&apps_smmu 0x1004 0x80>, <&apps_smmu 0x1044 0x20>; + dma-coherent; }; compute-cb@5 { @@ -4824,6 +4826,7 @@ iommus = <&apps_smmu 0x1005 0x80>, <&apps_smmu 0x1045 0x20>; + dma-coherent; }; compute-cb@6 { @@ -4832,6 +4835,7 @@ iommus = <&apps_smmu 0x1006 0x80>, <&apps_smmu 0x1046 0x20>; + dma-coherent; }; compute-cb@7 { @@ -4841,6 +4845,7 @@ iommus = <&apps_smmu 0x1007 0x40>, <&apps_smmu 0x1067 0x0>, <&apps_smmu 0x1087 0x0>; + dma-coherent; }; }; @@ -4961,6 +4966,7 @@ iommus = <&apps_smmu 0x1961 0x0>, <&apps_smmu 0x0c01 0x20>, <&apps_smmu 0x19c1 0x0>; + dma-coherent; }; compute-cb@2 { @@ -4970,6 +4976,7 @@ iommus = <&apps_smmu 0x1962 0x0>, <&apps_smmu 0x0c02 0x20>, <&apps_smmu 0x19c2 0x0>; + dma-coherent; }; compute-cb@3 { @@ -4979,6 +4986,7 @@ iommus = <&apps_smmu 0x1963 0x0>, <&apps_smmu 0x0c03 0x20>, <&apps_smmu 0x19c3 0x0>; + dma-coherent; }; compute-cb@4 { @@ -4988,6 +4996,7 @@ iommus = <&apps_smmu 0x1964 0x0>, <&apps_smmu 0x0c04 0x20>, <&apps_smmu 0x19c4 0x0>; + dma-coherent; }; compute-cb@5 { @@ -4997,6 +5006,7 @@ iommus = <&apps_smmu 0x1965 0x0>, <&apps_smmu 0x0c05 0x20>, <&apps_smmu 0x19c5 0x0>; + dma-coherent; }; compute-cb@6 { @@ -5006,6 +5016,7 @@ iommus = <&apps_smmu 0x1966 0x0>, <&apps_smmu 0x0c06 0x20>, <&apps_smmu 0x19c6 0x0>; + dma-coherent; }; compute-cb@7 { @@ -5015,6 +5026,7 @@ iommus = <&apps_smmu 0x1967 0x0>, <&apps_smmu 0x0c07 0x20>, <&apps_smmu 0x19c7 0x0>; + dma-coherent; }; compute-cb@8 { @@ -5024,6 +5036,7 @@ iommus = <&apps_smmu 0x1968 0x0>, <&apps_smmu 0x0c08 0x20>, <&apps_smmu 0x19c8 0x0>; + dma-coherent; }; }; }; -- 2.17.1