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[147.75.199.223]) by mx.google.com with ESMTPS id t2-20020a05620a004200b0077dc8b9a69esi12450014qkt.698.2024.01.25.03.18.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 03:18:25 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-38496-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) client-ip=147.75.199.223; Authentication-Results: mx.google.com; arc=pass (i=1 spf=pass spfdomain=arm.com dmarc=pass fromdomain=arm.com); spf=pass (google.com: domain of linux-kernel+bounces-38496-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-38496-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id 722481C2092D for ; Thu, 25 Jan 2024 11:18:25 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CDC713D55F; Thu, 25 Jan 2024 11:17:47 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 98A0D41742; Thu, 25 Jan 2024 11:17:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706181467; cv=none; b=UBKqLbbwndGAubcjzYO1CxsPO+5jKjqkam9lV+qoY6/u+DZBOeelE2r+3iipJRdZGpMY84o6IPSpERG4rN1BMtCUAotmqhxW7gq70VnT6vNUKSwu/eUaDYcAJZEUmk0xQ3aHOnCBm9lEQyg4XJswnUhW+YqqvdDR9XidzogdHxE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706181467; c=relaxed/simple; bh=igm/h/zmoLbXL5iWQEwPa7zebeNK6VDp4ngPTNMXweg=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=bk6kbY7G+rV58AV0wE1z3LlhT3TRcVK0oW+gt6LIg0PHwej0AS6Kwlzn45IDjU3mzZ06blqS8LSK4eIjyW/PNDLYhbyzDk7EGxFrpFP0EctwX3HKyXifaTAJX7QMKYMqkMAKac7Zs4eXAj0o/Rjaz4lQvZHZbjATWoEN4ewMDXo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6DC181477; Thu, 25 Jan 2024 03:18:29 -0800 (PST) Received: from bogus (unknown [10.57.78.12]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3D7673F73F; Thu, 25 Jan 2024 03:17:41 -0800 (PST) Date: Thu, 25 Jan 2024 11:17:38 +0000 From: Sudeep Holla To: Ricardo Neri Cc: x86@kernel.org, Andreas Herrmann , Catalin Marinas , Chen Yu , Len Brown , Sudeep Holla , Radu Rendec , Pierre Gondois , Pu Wen , "Rafael J. Wysocki" , Srinivas Pandruvada , Will Deacon , Zhang Rui , Huang Ying , "Ravi V. Shankar" , stable@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 0/4] x86/cacheinfo: Set the number of leaves per CPU Message-ID: <20240125111738.4otb55z2pj7ddtpk@bogus> References: <20231212222519.12834-1-ricardo.neri-calderon@linux.intel.com> <20240125025652.GA15039@ranerica-svr.sc.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240125025652.GA15039@ranerica-svr.sc.intel.com> On Wed, Jan 24, 2024 at 06:56:52PM -0800, Ricardo Neri wrote: > On Tue, Dec 12, 2023 at 02:25:15PM -0800, Ricardo Neri wrote: > > Hi, > > > > The interface /sys/devices/system/cpu/cpuX/cache is broken (not populated) > > if CPUs have different numbers of subleaves in CPUID 4. This is the case > > of Intel Meteor Lake. > > Hello. Wondering if there is any feedback on this patchset. The interface > /sys/devices/system/cpu/cpuX/cache is still broken on Meteor Lake with > v6.8-rc1. > > I verified that this patchset applies cleanly on v6.8-rc1. > Sorry I though I had acked it but now I see 1/4 is new in v4. I have responded on the original patch. -- Regards, Sudeep