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Date: Thu, 25 Jan 2024 12:53:24 +0100
Message-Id: <CYNRLZ2XTOGY.3ANWB33IDCN2W@bootlin.com>
Cc: "Vladimir Kondratiev" <vladimir.kondratiev@mobileye.com>,
 <linux-mips@vger.kernel.org>, <linux-clk@vger.kernel.org>,
 <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, "Thomas
 Petazzoni" <thomas.petazzoni@bootlin.com>, "Tawfik Bayouk"
 <tawfik.bayouk@mobileye.com>, <linux-gpio@vger.kernel.org>
To: "Krzysztof Kozlowski" <krzysztof.kozlowski@linaro.org>, "Gregory
 CLEMENT" <gregory.clement@bootlin.com>, "Michael Turquette"
 <mturquette@baylibre.com>, "Stephen Boyd" <sboyd@kernel.org>, "Rob Herring"
 <robh+dt@kernel.org>, "Krzysztof Kozlowski"
 <krzysztof.kozlowski+dt@linaro.org>, "Conor Dooley" <conor+dt@kernel.org>,
 "Thomas Bogendoerfer" <tsbogend@alpha.franken.de>, "Linus Walleij"
 <linus.walleij@linaro.org>, =?utf-8?q?Rafa=C5=82_Mi=C5=82ecki?=
 <rafal@milecki.pl>, "Philipp Zabel" <p.zabel@pengutronix.de>
From: =?utf-8?q?Th=C3=A9o_Lebrun?= <theo.lebrun@bootlin.com>
Subject: Re: [PATCH v3 08/17] clk: eyeq5: add platform driver
References: <20240123-mbly-clk-v3-0-392b010b8281@bootlin.com>
 <20240123-mbly-clk-v3-8-392b010b8281@bootlin.com>
 <127fd51b-cd64-4e00-99d6-7be9b79f2dcc@linaro.org>
 <CYN33YJ10HYS.2YDXB158LFZPL@bootlin.com>
 <001993b9-ea0c-49c3-a4e5-4cea10c54082@linaro.org>
In-Reply-To: <001993b9-ea0c-49c3-a4e5-4cea10c54082@linaro.org>

Hi,

On Thu Jan 25, 2024 at 8:46 AM CET, Krzysztof Kozlowski wrote:
> On 24/01/2024 17:41, Th=C3=A9o Lebrun wrote:
> > Hello,
> >=20
> > On Wed Jan 24, 2024 at 8:05 AM CET, Krzysztof Kozlowski wrote:
> >> On 23/01/2024 19:46, Th=C3=A9o Lebrun wrote:
> >>> Add the Mobileye EyeQ5 clock controller driver. It might grow to add
> >>> support for other platforms from Mobileye.
> >>>
> >>> It handles 10 read-only PLLs derived from the main crystal on board. =
It
> >>> exposes a table-based divider clock used for OSPI. Other platform
> >>> clocks are not configurable and therefore kept as fixed-factor
> >>> devicetree nodes.
> >>>
> >>> Two PLLs are required early on and are therefore registered at
> >>> of_clk_init(). Those are pll-cpu for the GIC timer and pll-per for th=
e
> >>> UARTs.
> >>>
> >>
> >>
> >>> +#define OLB_PCSR1_RESET				BIT(0)
> >>> +#define OLB_PCSR1_SSGC_DIV			GENMASK(4, 1)
> >>> +/* Spread amplitude (% =3D 0.1 * SPREAD[4:0]) */
> >>> +#define OLB_PCSR1_SPREAD			GENMASK(9, 5)
> >>> +#define OLB_PCSR1_DIS_SSCG			BIT(10)
> >>> +/* Down-spread or center-spread */
> >>> +#define OLB_PCSR1_DOWN_SPREAD			BIT(11)
> >>> +#define OLB_PCSR1_FRAC_IN			GENMASK(31, 12)
> >>> +
> >>> +static struct clk_hw_onecell_data *eq5c_clk_data;
> >>> +static struct regmap *eq5c_olb;
> >>
> >> Drop these two. No file-scope regmaps for drivers. Use private contain=
er
> >> structures.
> >=20
> > I wouldn't know how to handle the two steps then. Two clocks and the cl=
k
> > provider are registered at of_clk_init() using CLK_OF_DECLARE_DRIVER().
>
> Right, if some clocks have to be early, CLK_OF_DECLARE_DRIVER needs
> static ones. But your commit subject says it is a platform driver and
> all other pieces of this code is rather incompatible with this approach.

That is my bad on the commit subject. What do you refer to by "all other
pieces of this code is rather incompatible with this approach"?

I've tried to minimise the use of static variables. Therefore as soon as
the probe is started, we switch to the usual way of using a private
struct that contains our info.

>
> Do not use CLK_OF_DECLARE_DRIVER for cases where you have dependencies
> because it forces you to manually order initcalls, which is exactly what
> we do not want.

What should I be using? I got confirmation from Stephen that this
mixture of CLK_OF_DECLARE_DRIVER() + platform driver is what I should
be using as review in my V1.

https://lore.kernel.org/lkml/fa32e6fae168e10d42051b89197855e9.sboyd@kernel.=
org/

>
>
> > The rest is at platform device probe. Without a static, there are no
> > way to pass the struct clk_hw_onecell_data from one to the other.
> >=20
> > I've looked at all clock drivers that do CLK_OF_DECLARE_DRIVER() and
> > register a platform driver.
>
> Even though the code is correct, using arguments "other did it" will not
> work. You want to say that you implement legacy, poor code because you
> saw legacy, poor code?

Yes I see what you mean. It's just that this is not the sort of things
that are documented. And learning The Right Way(TM) when you don't know
it can only be done by looking at existing stuff. I'm being exhaustive
to avoid basing my approach on one old-school driver that is using the
wrong approach.

> >> ...
> >>
> >>> +static void __init eq5c_init(struct device_node *np)
> >>> +{
> >>> +	struct device_node *parent_np =3D of_get_parent(np);
> >>> +	int i, ret;
> >>> +
> >>> +	eq5c_clk_data =3D kzalloc(struct_size(eq5c_clk_data, hws, EQ5C_NB_C=
LKS),
> >>> +				GFP_KERNEL);
> >>> +	if (!eq5c_clk_data) {
> >>> +		ret =3D -ENOMEM;
> >>> +		goto err;
> >>> +	}
> >>> +
> >>> +	eq5c_clk_data->num =3D EQ5C_NB_CLKS;
> >>> +
> >>> +	/*
> >>> +	 * Mark all clocks as deferred. We register some now and others at
> >>> +	 * platform device probe.
> >>> +	 */
> >>> +	for (i =3D 0; i < EQ5C_NB_CLKS; i++)
> >>> +		eq5c_clk_data->hws[i] =3D ERR_PTR(-EPROBE_DEFER);
> >>> +
> >>> +	/*
> >>> +	 * Currently, if OLB is not available, we log an error, fail init t=
hen
> >>
> >> How it could be not available? Only with broken initcall ordering. Fix
> >> your initcall ordering and then simplify all this weird code.
> >=20
> > of_syscon_register() and regmap_init_mmio() lists many reasons for
> > it to not be available. Am I missing something?
>
> Yes, initcall ordering.

You said the regmap can only not be available with broken initcall
ordering. I say that is not the only reason.

About initcall, I've removed those that used initcall in the three
drivers I'm using except this clk one that requires two clocks at
of_clk_init().

Thanks,

--
Th=C3=A9o Lebrun, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com