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Date: Thu, 25 Jan 2024 05:07:47 -0800
From: "H. Peter Anvin" <hpa@zytor.com>
To: Andi Kleen <ak@linux.intel.com>,
        "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
CC: Thomas Gleixner <tglx@linutronix.de>, Ingo Molnar <mingo@redhat.com>,
        Borislav Petkov <bp@alien8.de>,
        Dave Hansen <dave.hansen@linux.intel.com>, x86@kernel.org,
        linux-kernel@vger.kernel.org, Kai Huang <kai.huang@intel.com>,
        Sean Christopherson <seanjc@google.com>
Subject: =?US-ASCII?Q?Re=3A_=5BPATCHv3=2C_RESEND=5D_x86/trampoline=3A_Bypass_co?= =?US-ASCII?Q?mpat_mode_in_trampoline=5Fstart64=28=29_if_not_needed?=
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On January 25, 2024 1:57:18 AM PST, Andi Kleen <ak@linux=2Eintel=2Ecom> wro=
te:
>> +	/* Paging mode is correct proceed in 64-bit mode */
>> +
>> +	LOCK_AND_LOAD_REALMODE_ESP lock_rip=3D1
>> +
>> +	movw	$__KERNEL_DS, %dx
>> +	movl	%edx, %ss
>> +	addl	$pa_real_mode_base, %esp
>> +	movl	%edx, %ds
>> +	movl	%edx, %es
>> +	movl	%edx, %fs
>> +	movl	%edx, %gs
>> +
>> +	movl	$pa_trampoline_pgd, %eax
>> +	movq	%rax, %cr3
>> +
>> +	jmpq	*tr_start(%rip)
>
>Still think we should add a far jump here so that we run on a defined
>code segment=2E It probably doesn't matter since there are likely no
>IRETs before reloading anyways, but it seems cleaner=2E
>
>-Andi
>

Agreed=2E