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From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Date: Thu, 25 Jan 2024 15:25:23 +0200
Message-ID: <CAA8EJpoEMsrEp02pLpceMx7fr-j9=xVDiUYt1SKHsF4YCmfvAQ@mail.gmail.com>
Subject: Re: [PATCH 2/6] arm64: dts: qcom: sm8250: describe all PCI MSI interrupts
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: Bjorn Andersson <andersson@kernel.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, 
	Rob Herring <robh+dt@kernel.org>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, 
	linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, 
	linux-kernel@vger.kernel.org
Content-Type: text/plain; charset="UTF-8"

On Thu, 25 Jan 2024 at 15:18, Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
>
> On Thu, 25 Jan 2024 at 15:07, Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
> >
> > Each group of MSI interrupts is mapped to the separate host interrupt.
> > Describe each of interrupts in the device tree for PCIe hosts.  Not
> > tested on hardware.
> >
> > PCIe0 was done already in commit f2819650aab5 ("arm64: dts: qcom:
> > sm8250: provide additional MSI interrupts").
> >
> > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> > ---
> >  arch/arm64/boot/dts/qcom/sm8250.dtsi | 24 ++++++++++++++++++++----
> >  1 file changed, 20 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> > index 760501c1301a..41f5e6eb2f6b 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> > @@ -2248,8 +2248,16 @@ pcie1: pcie@1c08000 {
> >                         ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
> >                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
> >
> > -                       interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
> > -                       interrupt-names = "msi";
> > +                       interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
> > +                       interrupt-names = "msi0", "msi1", "msi2", "msi3",
> > +                                         "msi4", "msi5", "msi6", "msi7";
> >                         #interrupt-cells = <1>;
> >                         interrupt-map-mask = <0 0 0 0x7>;
> >                         interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> > @@ -2349,8 +2357,16 @@ pcie2: pcie@1c10000 {
> >                         ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
> >                                  <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
> >
> > -                       interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
> > -                       interrupt-names = "msi";
> > +                       interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
> > +                       interrupt-names = "msi0", "msi1", "msi2", "msi3",
> > +                                         "msi4", "msi5", "msi6", "msi7";
>
> This part looks a bit suspicious. All other platforms have these
> interrupts in a continuous range.

Hmm, pcie1 interrupts are also not contiguous. Okay, fine then:

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

-- 
With best wishes
Dmitry