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Thu, 25 Jan 2024 07:45:41 -0800 (PST) X-Gm-Message-State: AOJu0Yz5HErKUbrEKk4by9ixmD2KvqFzuIar86/F5Kc9H5hE3oJXfoIl pjEHL0ExtRq2VzqAxxFOfZOCaITtNOaLQBNfVkGCWyv4psbvtn9YCsTA1u1BUgf66KYdvCSN2eH vx1kngwP/upzhHuHSvr5pCT2jv9I= X-Received: by 2002:a05:6a20:432b:b0:19a:fa18:c306 with SMTP id h43-20020a056a20432b00b0019afa18c306mr1213214pzk.6.1706197541181; Thu, 25 Jan 2024 07:45:41 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240122170518.3090814-1-wens@kernel.org> <20240122170518.3090814-5-wens@kernel.org> <20240123004010.59cac5ad@minigeek.lan> <20240125150942.2535a228@donnerap.manchester.arm.com> In-Reply-To: <20240125150942.2535a228@donnerap.manchester.arm.com> Reply-To: wens@kernel.org From: Chen-Yu Tsai Date: Thu, 25 Jan 2024 23:45:29 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 4/7] dt-bindings: dma: allwinner,sun50i-a64-dma: Add compatible for H616 To: Andre Przywara Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jernej Skrabec , Samuel Holland , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Vinod Koul , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-sound@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, Jan 25, 2024 at 11:09=E2=80=AFPM Andre Przywara wrote: > > On Thu, 25 Jan 2024 22:37:34 +0800 > Chen-Yu Tsai wrote: > > Hi, > > > On Tue, Jan 23, 2024 at 8:41=E2=80=AFAM Andre Przywara wrote: > > > > > > On Tue, 23 Jan 2024 01:05:15 +0800 > > > Chen-Yu Tsai wrote: > > > > > > Hi, > > > > > > > From: Chen-Yu Tsai > > > > > > > > The DMA controllers found on the H616 and H618 are the same as the = one > > > > found on the H6. The only difference is the DMA endpoint (DRQ) layo= ut. > > > > > > That does not seem to be entirely true: The H616 encodes the two lowe= st > > > bits in DMA_DESC_ADDR_REG differently: on the H6 they must be 0 (word > > > aligned), on the H616 these contain bits [33:32] of the address of th= e > > > DMA descriptor. The manual doesn't describe the descriptor format in > > > much detail, but ec31c5c59492 suggests that those two bits are put in > > > the "para" word of the descriptor. > > > > Good catch. So, same as the A100 I believe? > > Yes, that's what I got as well. > > > > The good thing it that this encoding is backwards compatible, so I > > > think the fallback string still holds: Any driver just implementing t= he > > > H6 encoding would be able to drive the H616. > > > > > > I think the A100 was mis-described, as mentioned here: > > > https://lore.kernel.org/linux-arm-kernel/29e575b6-14cb-73f1-512d-9f0f= 934490ea@arm.com/ > > > I think we should: > > > - make the A100 use: "allwinner,sun50i-a100-dma", "sun50i-h6-dma" > > > - make the H616 use: "allwinner,sun50i-h616-dma", "allwinner,sun50i-a= 100-dma", "sun50i-h6-dma" > > > > > > Does that make sense? > > > > I wouldn't call that exactly backward compatible. Say the driver forgot= to > > clear the two bits. It would work fine on the H6, but the accessed addr= ess > > could be way off on the A100 and H616. > > I don't know the exact boundaries of "compatible" here, but the H6 manual > pretty clearly states "The descriptor address must be word-aligned." > But since the A100 compatible is known and supported for a while, that > doesn't really matter, practically speaking, I guess. I'd say that makes the descriptor address register backward compatible, > One could check how the H6 DMA controller reacts to those bits not being > 0, not sure if I find the time, though. but no idea about the parameter field in the descriptor. So for now I think we should just be cautious. Since as you mentioned the A100 is alread= y supported and listed separately, lets just keep that for now. ChenYu [...]