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Date: Thu, 25 Jan 2024 17:20:59 +0000
From: Conor Dooley <conor@kernel.org>
To: "Peng Fan (OSS)" <peng.fan@oss.nxp.com>
Cc: Jassi Brar <jassisinghbrar@gmail.com>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Dong Aisheng <aisheng.dong@nxp.com>,
	Shawn Guo <shawnguo@kernel.org>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	Fabio Estevam <festevam@gmail.com>,
	NXP Linux Team <linux-imx@nxp.com>, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	Peng Fan <peng.fan@nxp.com>
Subject: Re: [PATCH v4 1/4] dt-bindings: mailbox: fsl,mu: add i.MX95
 Generic/ELE/V2X MU compatible
Message-ID: <20240125-prudishly-contort-274a48bbb33e@spud>
References: <20240125-imx-mailbox-v4-0-800be5383c20@nxp.com>
 <20240125-imx-mailbox-v4-1-800be5383c20@nxp.com>
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On Thu, Jan 25, 2024 at 01:20:03PM +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>=20
> Add i.MX95 Generic, Secure Enclave and V2X Message Unit compatible string.
> And some MUs has internal RAMs for SCMI shared buffer usage.

Please restrict the SRAM child none to whatever the "some MUs" are that
actually have it.

Thanks,
Conor.

>=20
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  .../devicetree/bindings/mailbox/fsl,mu.yaml        | 52 ++++++++++++++++=
+++++-
>  1 file changed, 50 insertions(+), 2 deletions(-)
>=20
> diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml b/Docu=
mentation/devicetree/bindings/mailbox/fsl,mu.yaml
> index 12e7a7d536a3..86759831b24a 100644
> --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
> +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
> @@ -29,10 +29,14 @@ properties:
>        - const: fsl,imx8ulp-mu
>        - const: fsl,imx8-mu-scu
>        - const: fsl,imx8-mu-seco
> -      - const: fsl,imx93-mu-s4
>        - const: fsl,imx8ulp-mu-s4
> +      - const: fsl,imx93-mu-s4
> +      - const: fsl,imx95-mu-ele
> +      - const: fsl,imx95-mu-v2x
>        - items:
> -          - const: fsl,imx93-mu
> +          - enum:
> +              - fsl,imx93-mu
> +              - fsl,imx95-mu
>            - const: fsl,imx8ulp-mu
>        - items:
>            - enum:
> @@ -95,6 +99,19 @@ properties:
>    power-domains:
>      maxItems: 1
> =20
> +  ranges: true
> +
> +  '#address-cells':
> +    const: 1
> +
> +  '#size-cells':
> +    const: 1
> +
> +patternProperties:
> +  "^sram@[a-f0-9]+":
> +    $ref: /schemas/sram/sram.yaml#
> +    unevaluatedProperties: false
> +
>  required:
>    - compatible
>    - reg
> @@ -134,3 +151,34 @@ examples:
>          interrupts =3D <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
>          #mbox-cells =3D <2>;
>      };
> +
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    mu2: mailbox@445b0000 {
> +        compatible =3D "fsl,imx95-mu", "fsl,imx8ulp-mu";
> +        reg =3D <0x445b0000 0x10000>;
> +        ranges;
> +        interrupts =3D <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
> +        #address-cells =3D <1>;
> +        #size-cells =3D <1>;
> +        #mbox-cells =3D <2>;
> +
> +        sram@445b1000 {
> +            compatible =3D "mmio-sram";
> +            reg =3D <0x445b1000 0x400>;
> +            ranges =3D <0x0 0x445b1000 0x400>;
> +            #address-cells =3D <1>;
> +            #size-cells =3D <1>;
> +
> +            scmi_buf0: scmi-sram-section@0 {
> +                compatible =3D "arm,scmi-shmem";
> +                reg =3D <0x0 0x80>;
> +            };
> +
> +            scmi_buf1: scmi-sram-section@80 {
> +                compatible =3D "arm,scmi-shmem";
> +                reg =3D <0x80 0x80>;
> +            };
> +        };
> +    };
>=20
> --=20
> 2.37.1
>=20

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