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Thu, 25 Jan 2024 09:23:01 -0800 Date: Thu, 25 Jan 2024 09:23:00 -0800 From: Nicolin Chen To: Jason Gunthorpe CC: "will@kernel.org" , Robin Murphy , "joro@8bytes.org" , "jean-philippe@linaro.org" , Alistair Popple , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "iommu@lists.linux.dev" Subject: Re: [PATCH 1/3] iommu/io-pgtable-arm: Add nents_per_pgtable in struct io_pgtable_cfg Message-ID: References: <61f9b371-7c45-26b1-ec0f-600765280c89@arm.com> <20240122130152.GP734935@nvidia.com> <20240122175700.GB1455070@nvidia.com> <20240125135537.GP1455070@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20240125135537.GP1455070@nvidia.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CF:EE_|DS0PR12MB8200:EE_ X-MS-Office365-Filtering-Correlation-Id: 50ee553d-93fa-4f98-9004-08dc1dca5238 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: mB9EpIMItV+bpjG3pqdY5Qnkqy+Ihc8qP6HGkje1qJKehHG3erjzrDWPC7oqZt3SwsurUkNOiqGPhNif11ZiyVh97q/xijCp3dl9Gdp8dkL8Sp0npDs+BMWdHr9bb2k9u+iLYQSR2195LS43U9i9tffoKpjIrLuHZmbNNxV8UeNvMWUPz9aEuRbRuVIf9vfKsaDZ+MgyKXi4Y952KQpVS0PelEzUmHhU3ZCaXKh2UDub3qATMT4nKUR+8x5tvPh+cd0GmFONfMhxrkw2dkZMGQTbbU3VB32SrkFNVfp32/oIl4pDnZzciEaIxqemoomC0uq4IjrOamd2sIuzdZEmnatqgmwr/uVzVjpIgfzZLBq2hZ0VNkXOhKE9Mhk3Stfl8auV4WxpmSCjTTCOQvgnHAMDGSWfJ3fkXeQwr8cUAag/1zkkW6ZnpRj2x8EYuZMhG7HGzHdyh2REXN6L94zz6PD0aisr3FqtOoKvytYahEe8uB+LLxFQQGeFwnE+NQNKv/06aVJbk7QHhgLhb58J4M1ezS4egtzqMAgta3YB+W6f5hzYPOAnjkmGzSBn0LjbWPWd5oZ20domMhxPDznsF5qqq9Yh37DhXHMoLn+ZmajZcbict/GEn9LWH2yj9QVeFOydNR/NlQWRsKMK3LbY2ZyuSUEhXZ7HWSgreLfzOn+aHQ11p0zTGfJeztaohkBLNhe39HDhBQhGUkpQBnBb+iorJf7eHmr2K61BUQs30jDZ9ZrLKQL3DR9c+tLwJ4Nm X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(396003)(136003)(346002)(376002)(230922051799003)(1800799012)(451199024)(82310400011)(186009)(64100799003)(46966006)(36840700001)(40470700004)(70586007)(316002)(54906003)(9686003)(26005)(70206006)(55016003)(6636002)(7636003)(82740400003)(478600001)(356005)(40460700003)(33716001)(40480700001)(8936002)(4326008)(8676002)(6862004)(5660300002)(47076005)(426003)(83380400001)(36860700001)(336012)(86362001)(2906002)(41300700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Jan 2024 17:23:17.8399 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 50ee553d-93fa-4f98-9004-08dc1dca5238 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8200 On Thu, Jan 25, 2024 at 09:55:37AM -0400, Jason Gunthorpe wrote: > On Tue, Jan 23, 2024 at 04:11:09PM -0800, Nicolin Chen wrote: > > > prevented strongly. Broadly speaking if SVA is pushing too high an > > > invalidation workload then we need to agressively trim it, and do so > > > dynamically. Certainly we should not have a tunable that has to be set > > > right to avoid soft lockup. > > > > > > A tunable to improve performance, perhaps, but not to achieve basic > > > correctness. > > > > So, should we make an optional tunable only for those who care > > about performance? Though I think having a tunable would just > > fix both issues. > > When the soft lockup issue is solved you can consider if a tunable is > still interesting.. Yea, it would be on top of the soft lockup fix. I assume we are still going with your change: arm_smmu_inv_range_too_big, though I wonder if we should apply before your rework series to make it a bug fix.. > > > Maybe it is really just a simple thing - compute how many invalidation > > > commands are needed, if they don't all fit in the current queue space, > > > then do an invalidate all instead? > > > > The queue could actually have a large space. But one large-size > > invalidation would be divided into batches that have to execute > > back-to-back. And the batch size is 64 commands in 64-bit case, > > which might be too small as a cap. > > Yes, some notable code reorganizing would be needed to implement > something like this > > Broadly I'd sketch sort of: > > - Figure out how fast the HW can execute a lot of commands > - The above should drive some XX maximum number of commands, maybe we > need to measure at boot, IDK > - Strongly time bound SVA invalidation: > * No more than XX commands, if more needed then push invalidate > all > * All commands must fit in the available queue space, if more > needed then push invalidate all > - The total queue depth must not be larger than YY based on the > retire rate so that even a full queue will complete invalidation > below the target time. > > A tunable indicating what the SVA time bound target should be might be > appropriate.. Thanks for listing it out. I will draft something with that, and should we just confine it to SVA or non DMA callers in general? Nicolin