Received-SPF: pass (google.com: domain of linux-kernel+bounces-39034-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1;
Date: Thu, 25 Jan 2024 17:24:33 +0000
From: Conor Dooley <conor@kernel.org>
To: Wenhua Lin <Wenhua.Lin@unisoc.com>
Cc: Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= <u.kleine-koenig@pengutronix.de>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Orson Zhai <orsonzhai@gmail.com>,
	Baolin Wang <baolin.wang@linux.alibaba.com>,
	Chunyan Zhang <zhang.lyra@gmail.com>, linux-pwm@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	wenhua lin <wenhua.lin1994@gmail.com>,
	Xiongpeng Wu <xiongpeng.wu@unisoc.com>,
	zhaochen su <zhaochen.su29@gmail.com>,
	Zhaochen Su <Zhaochen.Su@unisoc.com>,
	Xiaolong Wang <Xiaolong.Wang@unisoc.com>
Subject: Re: [PATCH V2 6/6] dt-bindings: pwm: sprd: Add sprd,mod attribute
Message-ID: <20240125-stammer-sandblast-0dcad9e535c0@spud>
References: <20240125025533.10315-1-Wenhua.Lin@unisoc.com>
 <20240125025533.10315-7-Wenhua.Lin@unisoc.com>
Precedence: bulk
MIME-Version: 1.0
Content-Type: multipart/signed; micalg=pgp-sha256;
	protocol="application/pgp-signature"; boundary="Ia640Mup0gRbyG16"
Content-Disposition: inline
In-Reply-To: <20240125025533.10315-7-Wenhua.Lin@unisoc.com>


--Ia640Mup0gRbyG16
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
Content-Transfer-Encoding: quoted-printable

On Thu, Jan 25, 2024 at 10:55:33AM +0800, Wenhua Lin wrote:
> Add sprd,mod attribute, which set the number of different
> duty cycles that PWM's waveform could output, to dts.
>=20
> Signed-off-by: Wenhua Lin <Wenhua.Lin@unisoc.com>
> ---
>  Documentation/devicetree/bindings/pwm/pwm-sprd.yaml | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>=20
> diff --git a/Documentation/devicetree/bindings/pwm/pwm-sprd.yaml b/Docume=
ntation/devicetree/bindings/pwm/pwm-sprd.yaml
> index 02e039fee3b4..7c956b840fa1 100644
> --- a/Documentation/devicetree/bindings/pwm/pwm-sprd.yaml
> +++ b/Documentation/devicetree/bindings/pwm/pwm-sprd.yaml
> @@ -55,6 +55,16 @@ properties:
>      minItems: 4
>      maxItems: 4
> =20
> +  sprd,mod:
> +    $ref: /schemas/types.yaml#/definitions/uint32-array
> +    minItems: 4
> +    maxItems: 4
> +    items:
> +      minimum: 0xFF
> +      maximum: 0xFFF
> +    description: |
> +      The number of different duty cycles that could be set for PWM's wa=
veform output.

Why is this not a fixed value for a given SoC? Given the description, it
certainly sounds like something that does not vary on a per device
basis.

Thanks,
Conor.

> +
>    "#pwm-cells":
>      const: 2
> =20
> @@ -63,6 +73,7 @@ required:
>    - reg
>    - clocks
>    - clock-names
> +  - sprd,mod
> =20
>  additionalProperties: false
> =20
> @@ -88,6 +99,7 @@ examples:
>                                   <&ext_26m>,
>                                   <&ext_26m>,
>                                   <&ext_26m>;
> +        sprd,mod =3D <0xFF 0x1FF 0x3FF 0xFFF>;
>          #pwm-cells =3D <2>;
>      };
> =20
> --=20
> 2.17.1
>=20

--Ia640Mup0gRbyG16
Content-Type: application/pgp-signature; name="signature.asc"

-----BEGIN PGP SIGNATURE-----

iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZbKZUQAKCRB4tDGHoIJi
0p/4APwOno17wR0ULk3ScAzUFUpYmnfhWHJD4AVnFP5xK4a2ZQEA1ePEUwebT2ZG
YtxYi+oxd1sm4IGeW4GQklWnv0hdBAY=
=24Fz
-----END PGP SIGNATURE-----

--Ia640Mup0gRbyG16--