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From: Qiang Yu <quic_qianyu@quicinc.com>
To: andersson@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, quic_cang@quicinc.com,
        quic_mrana@quicinc.com, quic_qianyu@quicinc.com
Subject: [PATCH] arm64: dts: qcom: aim300: Enable PCIe0 for WLAN
Date: Fri, 26 Jan 2024 16:22:28 +0800
Message-Id: <1706257348-638-1-git-send-email-quic_qianyu@quicinc.com>
Precedence: bulk

WLAN is connected to PCIe0 on aim300 board. Hence, enable PCIe0 to let
WLAN work.

Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
---
This change is tested and rebased on https://lore.kernel.org/linux-arm-msm/20240119100621.11788-7-quic_tengfan@quicinc.com/

 arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts b/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
index 20a3c97..d42cfac 100644
--- a/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
+++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300-aiot.dts
@@ -251,7 +251,7 @@
 
 &gcc {
 	clocks = <&bi_tcxo_div2>, <&sleep_clk>,
-		 <0>,
+		 <&pcie0_phy>,
 		 <&pcie1_phy>,
 		 <0>,
 		 <&ufs_mem_phy 0>,
@@ -349,6 +349,23 @@
 	status = "okay";
 };
 
+&pcie0 {
+	wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+	perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie0_default_state>;
+
+	status = "okay";
+};
+
+&pcie0_phy {
+	vdda-phy-supply = <&vreg_l1e_0p88>;
+	vdda-pll-supply = <&vreg_l3e_1p2>;
+
+	status = "okay";
+};
+
 &pm8550_flash {
 	status = "okay";
 
-- 
2.7.4