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From: Xiong Zhang <xiong.y.zhang@linux.intel.com>
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	xiong.y.zhang@linux.intel.com
Subject: [RFC PATCH 24/41] KVM: x86/pmu: Zero out unexposed Counters/Selectors to avoid information leakage
Date: Fri, 26 Jan 2024 16:54:27 +0800
Message-Id: <20240126085444.324918-25-xiong.y.zhang@linux.intel.com>
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From: Mingwei Zhang <mizhang@google.com>

Zero out unexposed counters/selectors because even though KVM intercepts
all accesses to unexposed PMU MSRs, it does pass through RDPMC instruction
which allows guest to read all GP counters and fixed counters. So, zero out
unexposed counter values which might contain critical information for the
host.

Signed-off-by: Mingwei Zhang <mizhang@google.com>
---
 arch/x86/kvm/vmx/pmu_intel.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
index f79bebe7093d..4b4da7f17895 100644
--- a/arch/x86/kvm/vmx/pmu_intel.c
+++ b/arch/x86/kvm/vmx/pmu_intel.c
@@ -895,11 +895,27 @@ static void intel_restore_pmu_context(struct kvm_vcpu *vcpu)
 		wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, pmc->eventsel);
 	}
 
+	/*
+	 * Zero out unexposed GP counters/selectors to avoid information leakage
+	 * since passthrough PMU does not intercept RDPMC.
+	 */
+	for (i = pmu->nr_arch_gp_counters; i < kvm_pmu_cap.num_counters_gp; i++) {
+		wrmsrl(MSR_IA32_PMC0 + i, 0);
+		wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0);
+	}
+
 	wrmsrl(MSR_CORE_PERF_FIXED_CTR_CTRL, pmu->fixed_ctr_ctrl);
 	for (i = 0; i < pmu->nr_arch_fixed_counters; i++) {
 		pmc = &pmu->fixed_counters[i];
 		wrmsrl(MSR_CORE_PERF_FIXED_CTR0 + i, pmc->counter);
 	}
+
+	/*
+	 * Zero out unexposed fixed counters to avoid information leakage
+	 * since passthrough PMU does not intercept RDPMC.
+	 */
+	for (i = pmu->nr_arch_fixed_counters; i < kvm_pmu_cap.num_counters_fixed; i++)
+		wrmsrl(MSR_CORE_PERF_FIXED_CTR0 + i, 0);
 }
 
 struct kvm_pmu_ops intel_pmu_ops __initdata = {
-- 
2.34.1