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charset=UTF-8 Content-Transfer-Encoding: 8bit On 25/01/2024 12:01, Théo Lebrun wrote: > Hello, > > On Thu Jan 25, 2024 at 8:51 AM CET, Krzysztof Kozlowski wrote: >> On 24/01/2024 16:14, Rob Herring wrote: >>>> + >>>> + pinctrl-b { >>>> + compatible = "mobileye,eyeq5-b-pinctrl"; >>>> + #pinctrl-cells = <1>; >>>> + }; >>>> + }; >>> >>> This can all be simplified to: >>> >>> system-controller@e00000 { >>> compatible = "mobileye,eyeq5-olb", "syscon"; >>> reg = <0xe00000 0x400>; >>> #reset-cells = <2>; >>> #clock-cells = <1>; >>> clocks = <&xtal>; >>> clock-names = "ref"; >>> >>> pins { ... }; >>> }; >>> >>> There is no need for sub nodes unless you have reusable blocks or each >>> block has its own resources in DT. >> >> Yes, however I believe there should be resources here: each subnode >> should get its address space. This is a bit tied to implementation, >> which currently assumes "everyone can fiddle with everything" in this block. >> >> Theo, can you draw memory map? > > It would be a mess. I've counted things up. The first 147 registers are > used in this 0x400 block. There are 31 individual blocks, with 7 > registers unused (holes to align next block). Holes are not really a problem. > > Functions are reset, clocks, LBIST, MBIST, DDR control, GPIO, > accelerator control, CPU entrypoint, PDTrace, IRQs, chip info & ID > stuff, control registers for PCIe / eMMC / Eth / SGMII / DMA / etc. So they are within separate blocks or not? Best regards, Krzysztof