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Fri, 26 Jan 2024 21:13:45 GMT Received: from [10.110.17.111] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Fri, 26 Jan 2024 13:13:44 -0800 Message-ID: Date: Fri, 26 Jan 2024 13:13:38 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [PATCH v12 04/41] usb: host: xhci-mem: Cleanup pending secondary event ring events Content-Language: en-US From: Wesley Cheng To: Mathias Nyman , , , , , , , , , , , , , , , , CC: , , , , , , References: <20240102214549.22498-1-quic_wcheng@quicinc.com> <20240102214549.22498-5-quic_wcheng@quicinc.com> <734591a1-50b4-6dc7-0b93-077355ec12e4@linux.intel.com> <7b2ec96b-b72f-c848-7c35-36e61a4072ac@quicinc.com> <2178e799-2068-7443-59b2-310dfdd1ddee@linux.intel.com> In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: I_bCQhXJsASqTNITaMpPE3gvQJrskugz X-Proofpoint-ORIG-GUID: I_bCQhXJsASqTNITaMpPE3gvQJrskugz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-25_14,2024-01-25_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 phishscore=0 spamscore=0 malwarescore=0 priorityscore=1501 mlxlogscore=820 impostorscore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 clxscore=1011 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401190000 definitions=main-2401260157 Hi Mathias, On 1/16/2024 12:24 PM, Wesley Cheng wrote: > Hi Mathias, > > On 1/15/2024 6:01 AM, Mathias Nyman wrote: >> On 10.1.2024 1.42, Wesley Cheng wrote: >>> Hi Mathias, >>> >>> On 1/8/2024 12:51 PM, Wesley Cheng wrote: >>>> Hi Mathias, >>>> >>>> On 1/4/2024 6:48 AM, Mathias Nyman wrote: >>>>> On 2.1.2024 23.45, Wesley Cheng wrote: >>>>>> As part of xHCI bus suspend, the XHCI is halted.  However, if >>>>>> there are >>>>>> pending events in the secondary event ring, it is observed that >>>>>> the xHCI >>>>>> controller stops responding to further commands upon host or device >>>>>> initiated bus resume.  Iterate through all pending events and >>>>>> update the >>>>>> dequeue pointer to the beginning of the event ring. >>>>>> >>>>>> Signed-off-by: Wesley Cheng >>>>> ... >>>>>> +/* >>>>>> + * Move the event ring dequeue pointer to skip events kept in the >>>>>> secondary >>>>>> + * event ring.  This is used to ensure that pending events in the >>>>>> ring are >>>>>> + * acknowledged, so the XHCI HCD can properly enter >>>>>> suspend/resume. The >>>>>> + * secondary ring is typically maintained by an external component. >>>>>> + */ >>>>>> +void xhci_skip_sec_intr_events(struct xhci_hcd *xhci, >>>>>> +    struct xhci_ring *ring,    struct xhci_interrupter *ir) >>>>>> +{ >>>>>> +    union xhci_trb *erdp_trb, *current_trb; >>>>>> +    u64 erdp_reg; >>>>>> +    u32 iman_reg; >>>>>> +    dma_addr_t deq; >>>>>> + >>>>>> +    /* disable irq, ack pending interrupt and ack all pending >>>>>> events */ >>>>>> +    xhci_disable_interrupter(ir); >>>>>> +    iman_reg = readl_relaxed(&ir->ir_set->irq_pending); >>>>>> +    if (iman_reg & IMAN_IP) >>>>>> +        writel_relaxed(iman_reg, &ir->ir_set->irq_pending); >>>>>> + >>>>>> +    /* last acked event trb is in erdp reg  */ >>>>>> +    erdp_reg = xhci_read_64(xhci, &ir->ir_set->erst_dequeue); >>>>>> +    deq = (dma_addr_t)(erdp_reg & ERST_PTR_MASK); >>>>>> +    if (!deq) { >>>>>> +        xhci_err(xhci, "event ring handling not required\n"); >>>>>> +        return; >>>>>> +    } >>>>>> + >>>>>> +    erdp_trb = current_trb = ir->event_ring->dequeue; >>>>>> +    /* read cycle state of the last acked trb to find out CCS */ >>>>>> +    ring->cycle_state = le32_to_cpu(current_trb->event_cmd.flags) >>>>>> & TRB_CYCLE; >>>>>> + >>>>>> +    while (1) { >>>>>> +        inc_deq(xhci, ir->event_ring); >>>>>> +        erdp_trb = ir->event_ring->dequeue; >>>>>> +        /* cycle state transition */ >>>>>> +        if ((le32_to_cpu(erdp_trb->event_cmd.flags) & TRB_CYCLE) != >>>>>> +            ring->cycle_state) >>>>>> +            break; >>>>>> +    } >>>>>> + >>>>>> +    xhci_update_erst_dequeue(xhci, ir, current_trb, true); >>>>>> +} >>>>> >>>>> Code above is very similar to the existing event ring processing >>>>> parts of xhci_irq() >>>>> and xhci_handle_event() >>>>> >>>>> I'll see if I can refactor the existing event ring processing, >>>>> decouple it from >>>>> event handling so that it could be used by primary and secondary >>>>> interrupters with >>>>> handlers, and this case where we just want to clear the event ring. >>>>> >>>> >>>> Thanks, that makes sense.  Will take a look as well. >>>> >>> >>> How about something like the below?  Tested this on my set up and >>> everything looks to be working fine.  Had to add another param to >>> struct xhci_interrupters to tell the XHCI interrupt handler to say if >>> that particular interrupter wants to skip_events (handling).  This >>> way, its something that the class driver utilizing the interrupter >>> will have to tell XHCI sideband.  It would allow the user to >>> determine if they want to use the interrupter to actually handle >>> events or not on the proc running Linux. >>> >> >> Yes, I have something similar. >> I'll share it soon, just need to >> clean it up a bit fist. >> > > Sure, no worries.  Will test it when its available.  Thanks! > Was just wondering if you had the time to clean up the changes? If not, maybe you can provide a patch with whatever you have, and I can try my best to clean it up to your liking? Thanks! Thanks Wesley Cheng