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From: yunhui cui <cuiyunhui@bytedance.com>
Date: Mon, 29 Jan 2024 09:29:12 +0800
Message-ID: <CAEEQ3wmVT_Lo3Jsoj-yp-3RCEfu=D7QKJq110sN-2a-wV+R59w@mail.gmail.com>
Subject: Re: [External] Re: [PATCH] RISC-V: add uniprocessor flush_tlb_range() support
To: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, 
	alexghiti@rivosinc.com, samuel.holland@sifive.com, ajones@ventanamicro.com, 
	mchitale@ventanamicro.com, dylan@andestech.com, 
	sergey.matyukevich@syntacore.com, prabhakar.mahadev-lad.rj@bp.renesas.com, 
	jszhang@kernel.org, apatel@ventanamicro.com, linux-riscv@lists.infradead.org, 
	linux-kernel@vger.kernel.org
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Hi Prabhakar,

On Sat, Jan 27, 2024 at 1:42=E2=80=AFAM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
>
> On Thu, Jan 25, 2024 at 6:23=E2=80=AFAM Yunhui Cui <cuiyunhui@bytedance.c=
om> wrote:
> >
> > Add support for flush_tlb_range() to improve TLB performance for
> > UP systems. In order to avoid the mutual inclusion of tlbflush.h
> > and hugetlb.h, the UP part is also implemented in tlbflush.c.
> >
> > Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
> > ---
> >  arch/riscv/include/asm/tlbflush.h |  61 ++++++----
> >  arch/riscv/mm/Makefile            |   2 +-
> >  arch/riscv/mm/tlbflush.c          | 195 ++++++++++++++++++------------
> >  3 files changed, 156 insertions(+), 102 deletions(-)
> >
> Boot tested with defconfig + rz/five enabled, no issues seen on
> RZ/Five SMARC EVK.
>
> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>

Thank you for testing !

Thanks=EF=BC=8C
Yunhui