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From: Alexandre Ghiti <alexghiti@rivosinc.com>
Date: Mon, 29 Jan 2024 09:28:31 +0100
Message-ID: <CAHVXubgjF9z6-0HpjPewaHsG-6ub1BC=E5sZaqVwcFXj=7R_pw@mail.gmail.com>
Subject: Re: [External] [PATCH -fixes] riscv: Flush the tlb when a page
 directory is freed
To: yunhui cui <cuiyunhui@bytedance.com>
Cc: Will Deacon <will@kernel.org>, "Aneesh Kumar K . V" <aneesh.kumar@linux.ibm.com>, 
	Andrew Morton <akpm@linux-foundation.org>, Nick Piggin <npiggin@gmail.com>, 
	Peter Zijlstra <peterz@infradead.org>, Paul Walmsley <paul.walmsley@sifive.com>, 
	Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, 
	Samuel Holland <samuel.holland@sifive.com>, Andrew Jones <ajones@ventanamicro.com>, 
	linux-arch@vger.kernel.org, linux-mm@kvack.org, 
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
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Hi Yunhui,

On Mon, Jan 29, 2024 at 4:07=E2=80=AFAM yunhui cui <cuiyunhui@bytedance.com=
> wrote:
>
> Hi Alexandre,
>
> On Sun, Jan 28, 2024 at 8:04=E2=80=AFPM Alexandre Ghiti <alexghiti@rivosi=
nc.com> wrote:
> >
> > The riscv privileged specification mandates to flush the TLB whenever a
> > page directory is modified, so add that to tlb_flush().
> >
> > Fixes: c5e9b2c2ae82 ("riscv: Improve tlb_flush()")
> > Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> > ---
> >  arch/riscv/include/asm/tlb.h | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/include/asm/tlb.h b/arch/riscv/include/asm/tlb.=
h
> > index 1eb5682b2af6..50b63b5c15bd 100644
> > --- a/arch/riscv/include/asm/tlb.h
> > +++ b/arch/riscv/include/asm/tlb.h
> > @@ -16,7 +16,7 @@ static void tlb_flush(struct mmu_gather *tlb);
> >  static inline void tlb_flush(struct mmu_gather *tlb)
> >  {
> >  #ifdef CONFIG_MMU
> > -       if (tlb->fullmm || tlb->need_flush_all)
> > +       if (tlb->fullmm || tlb->need_flush_all || tlb->freed_tables)
> >                 flush_tlb_mm(tlb->mm);
>
> Why is it necessary to flush all TLB entries of the process?

That's quite heavy but that's the only to flush any "intermediate"
cache that would cache non-leaf PTEs, the specification mentions this:

"If software modifies a non-leaf PTE, it should execute SFENCE.VMA
with rs1=3Dx0. If any PTE along the traversal path had its G bit set,
rs2 must be x0; otherwise, rs2 should be set to the ASID for which the
translation is being modified."

That was the behaviour before commit c5e9b2c2ae82 ("riscv: Improve
tlb_flush()").

>
> Thanks,
> Yunhui