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Date: Mon, 29 Jan 2024 11:12:33 +0200
From: Abel Vesa <abel.vesa@linaro.org>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Andy Gross <agross@kernel.org>, Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konrad.dybcio@linaro.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>,
	linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
	Rajendra Nayak <quic_rjendra@quicinc.com>
Subject: Re: [PATCH v3 06/10] clk: qcom: clk-alpha-pll: Add support for zonda
 ole pll configure
Message-ID: <ZbdsAfLcx4CoJQY7@linaro.org>
References: <20240129-x1e80100-clock-controllers-v3-0-d96dacfed104@linaro.org>
 <20240129-x1e80100-clock-controllers-v3-6-d96dacfed104@linaro.org>
 <CAA8EJppBtc2HKcZ2sAgBm=+sxtisp-hsADp-ui6PRTRRixB8xw@mail.gmail.com>
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On 24-01-29 06:08:38, Dmitry Baryshkov wrote:
> On Mon, 29 Jan 2024 at 00:52, Abel Vesa <abel.vesa@linaro.org> wrote:
> >
> > From: Rajendra Nayak <quic_rjendra@quicinc.com>
> >
> > Zonda ole pll has as extra PLL_OFF_CONFIG_CTL_U2 register, hence add
> > support for it.
> >
> > Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
> > Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> > ---
> >  drivers/clk/qcom/clk-alpha-pll.c | 26 ++++++++++++++++++++++++++
> >  drivers/clk/qcom/clk-alpha-pll.h |  4 ++++
> >  2 files changed, 30 insertions(+)
> >
> > diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> > index 05898d2a8b22..85f8e2ad0b37 100644
> > --- a/drivers/clk/qcom/clk-alpha-pll.c
> > +++ b/drivers/clk/qcom/clk-alpha-pll.c
> > @@ -52,6 +52,7 @@
> >  #define PLL_CONFIG_CTL(p)      ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
> >  #define PLL_CONFIG_CTL_U(p)    ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
> >  #define PLL_CONFIG_CTL_U1(p)   ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
> > +#define PLL_CONFIG_CTL_U2(p)   ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U2])
> >  #define PLL_TEST_CTL(p)                ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
> >  #define PLL_TEST_CTL_U(p)      ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
> >  #define PLL_TEST_CTL_U1(p)     ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
> > @@ -228,6 +229,21 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
> >                 [PLL_OFF_ALPHA_VAL] = 0x24,
> >                 [PLL_OFF_ALPHA_VAL_U] = 0x28,
> >         },
> > +       [CLK_ALPHA_PLL_TYPE_ZONDA_OLE] =  {
> > +               [PLL_OFF_L_VAL] = 0x04,
> > +               [PLL_OFF_ALPHA_VAL] = 0x08,
> > +               [PLL_OFF_USER_CTL] = 0x0c,
> > +               [PLL_OFF_USER_CTL_U] = 0x10,
> > +               [PLL_OFF_CONFIG_CTL] = 0x14,
> > +               [PLL_OFF_CONFIG_CTL_U] = 0x18,
> > +               [PLL_OFF_CONFIG_CTL_U1] = 0x1c,
> > +               [PLL_OFF_CONFIG_CTL_U2] = 0x20,
> > +               [PLL_OFF_TEST_CTL] = 0x24,
> > +               [PLL_OFF_TEST_CTL_U] = 0x28,
> > +               [PLL_OFF_TEST_CTL_U1] = 0x2c,
> > +               [PLL_OFF_OPMODE] = 0x30,
> > +               [PLL_OFF_STATUS] = 0x3c,
> > +       },
> >  };
> >  EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
> >
> > @@ -2093,6 +2109,16 @@ const struct clk_ops clk_alpha_pll_zonda_ops = {
> >  };
> >  EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops);
> >
> > +const struct clk_ops clk_alpha_pll_zonda_ole_ops = {
> > +       .enable = clk_zonda_pll_enable,
> > +       .disable = clk_zonda_pll_disable,
> > +       .is_enabled = clk_trion_pll_is_enabled,
> > +       .recalc_rate = clk_trion_pll_recalc_rate,
> > +       .round_rate = clk_alpha_pll_round_rate,
> > +       .set_rate = clk_zonda_pll_set_rate,
> > +};
> > +EXPORT_SYMBOL(clk_alpha_pll_zonda_ole_ops);
> 
> Let's maybe follow the existing example and #define
> clk_alpha_pll_zonda_ole_ops clk_alpha_pl_zonda_ops ?
> See the defines at clk-alpha-pll.h

Thanks for reviewing.

Will do that in the new version.

> 
> LGTM otherwise
> 
> > +
> >  void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
> >                                  const struct alpha_pll_config *config)
> >  {
> > diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
> > index a1a75bb12fe8..99a3db9de4a1 100644
> > --- a/drivers/clk/qcom/clk-alpha-pll.h
> > +++ b/drivers/clk/qcom/clk-alpha-pll.h
> > @@ -21,6 +21,7 @@ enum {
> >         CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
> >         CLK_ALPHA_PLL_TYPE_AGERA,
> >         CLK_ALPHA_PLL_TYPE_ZONDA,
> > +       CLK_ALPHA_PLL_TYPE_ZONDA_OLE,
> >         CLK_ALPHA_PLL_TYPE_LUCID_EVO,
> >         CLK_ALPHA_PLL_TYPE_LUCID_OLE,
> >         CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
> > @@ -42,6 +43,7 @@ enum {
> >         PLL_OFF_CONFIG_CTL,
> >         PLL_OFF_CONFIG_CTL_U,
> >         PLL_OFF_CONFIG_CTL_U1,
> > +       PLL_OFF_CONFIG_CTL_U2,
> >         PLL_OFF_TEST_CTL,
> >         PLL_OFF_TEST_CTL_U,
> >         PLL_OFF_TEST_CTL_U1,
> > @@ -119,6 +121,7 @@ struct alpha_pll_config {
> >         u32 config_ctl_val;
> >         u32 config_ctl_hi_val;
> >         u32 config_ctl_hi1_val;
> > +       u32 config_ctl_hi2_val;
> >         u32 user_ctl_val;
> >         u32 user_ctl_hi_val;
> >         u32 user_ctl_hi1_val;
> > @@ -173,6 +176,7 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops;
> >
> >  extern const struct clk_ops clk_alpha_pll_zonda_ops;
> >  #define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops
> > +extern const struct clk_ops clk_alpha_pll_zonda_ole_ops;
> >
> >  extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;
> >  extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops;
> >
> > --
> > 2.34.1
> >
> 
> 
> -- 
> With best wishes
> Dmitry