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From: Esben Haabendal <esben@geanix.com>
To: rohan.g.thomas@intel.com
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Subject: Re: [PATCH net-next 2/2] net: stmmac: TBS support for platform driver
In-Reply-To: <20240126173925.16794-1-rohan.g.thomas@intel.com> (rohan g.
	thomas's message of "Sat, 27 Jan 2024 01:39:25 +0800")
References: <87v87g4hmy.fsf@geanix.com>
	<20240126173925.16794-1-rohan.g.thomas@intel.com>
Date: Mon, 29 Jan 2024 11:11:17 +0100
Message-ID: <87plxktpoa.fsf@geanix.com>
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rohan.g.thomas@intel.com writes:

> From: Rohan G Thomas <rohan.g.thomas@intel.com>
>
> On Fri, 26 Jan 2024 09:35:01 +0100, Esben Haabendal wrote:
>
>> > +	/* If TBS feature is supported(i.e. tbssel is true), then at least 1 Tx
>> > +	 * DMA channel supports TBS. So if tbs_ch_num is 0 and tbssel is true,
>> > +	 * assume all Tx DMA channels support TBS. TBS_CH field, which gives
>> > +	 * number of Tx DMA channels with TBS support is only available only
>> for
>> > +	 * DW xGMAC IP. For other DWMAC IPs all Tx DMA channels can
>> support TBS.
>> 
>> The Ethernet QOS controllers found in various i.MX socs does not support TBS
>> on TX queue 0. I believe this patch would break the dwmac driver for these
>> platforms.
>
> AFAIU from Synopsys DWMAC5 Databook, all queues support TBS. But TBS
> cannot coexist with TSO. So all glue drivers enabling TBS feature are
> avoiding queue 0 to support TSO. Also packets requesting TSO are
> always directed to queue 0 by stmmac driver.

After re-reading the i.MX8MP documentation, and making a few
experiments, I have to agree with you. Enabling TBS (enhanced
descriptors) for Q0 should be ok on i.MX.

>> > --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
>> > +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
>> > @@ -3773,12 +3773,18 @@ stmmac_setup_dma_desc(struct stmmac_priv
>> *priv, unsigned int mtu)
>> >  		dma_conf->dma_rx_size = DMA_DEFAULT_RX_SIZE;
>> >
>> >  	/* Earlier check for TBS */
>> > -	for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) {
>> > -		struct stmmac_tx_queue *tx_q = &dma_conf-
>> >tx_queue[chan];
>> > -		int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en;
>> > +	if (priv->dma_cap.tbssel) {
>> > +		/* TBS is available only for tbs_ch_num of Tx DMA channels,
>> > +		 * starting from the highest Tx DMA channel.
>> > +		 */
>> > +		chan = priv->dma_cap.number_tx_channel - priv-
>> >dma_cap.tbs_ch_num;
>
> For IPs which don't have tbs_ch_num, this loop goes from 0 to
> number_tx_channel to check if tbs_enable is set by glue driver.
> Existing logic is also the same. Unless you set tbs_en flag of
> queue 0 from the glue driver or dts configuration this patch doesn't
> set tbs flag for queue 0. This is a sanity check to avoid wrong
> configuration for IPs which support tbs only in a few number of
> queues.

Sounds good.

>> > +		for (; chan < priv->plat->tx_queues_to_use; chan++) {
>> > +			struct stmmac_tx_queue *tx_q = &dma_conf-
>> >tx_queue[chan];
>> > +			int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en;
>> >
>> > -		/* Setup per-TXQ tbs flag before TX descriptor alloc */
>> > -		tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0;
>> > +			/* Setup per-TXQ tbs flag before TX descriptor alloc
>> */
>> > +			tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0;
>> > +		}
>> >  	}
>
> Please correct me if I've misstated anything.

No corrections for now :)

/Esben