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From: Frank Li <frank.li@nxp.com>
To: Xu Yang <xu.yang_2@nxp.com>, "will@kernel.org" <will@kernel.org>,
	"mark.rutland@arm.com" <mark.rutland@arm.com>, "robh+dt@kernel.org"
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CC: dl-linux-imx <linux-imx@nxp.com>, "mike.leach@linaro.org"
	<mike.leach@linaro.org>, "leo.yan@linaro.org" <leo.yan@linaro.org>,
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	<linux-kernel@vger.kernel.org>, "linux-perf-users@vger.kernel.org"
	<linux-perf-users@vger.kernel.org>
Subject: RE: [PATCH v3 2/4] perf: imx_perf: add support for i.MX95 platform
Thread-Topic: [PATCH v3 2/4] perf: imx_perf: add support for i.MX95 platform
Thread-Index: AQHaUpsTO+M/KRVAmUedkCPGjgxuk7Dw+qRw
Date: Mon, 29 Jan 2024 16:28:28 +0000
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> -----Original Message-----
> From: Xu Yang <xu.yang_2@nxp.com>
> Sent: Monday, January 29, 2024 4:15 AM
> To: Frank Li <frank.li@nxp.com>; will@kernel.org; mark.rutland@arm.com;
> robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> conor+dt@kernel.org; shawnguo@kernel.org; s.hauer@pengutronix.de;
> kernel@pengutronix.de; festevam@gmail.com; john.g.garry@oracle.com;
> jolsa@kernel.org; namhyung@kernel.org; irogers@google.com
> Cc: dl-linux-imx <linux-imx@nxp.com>; mike.leach@linaro.org;
> leo.yan@linaro.org; peterz@infradead.org; mingo@redhat.com;
> acme@kernel.org; alexander.shishkin@linux.intel.com;
> adrian.hunter@intel.com; Xu Yang <xu.yang_2@nxp.com>; linux-arm-
> kernel@lists.infradead.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-perf-users@vger.kernel.org
> Subject: [PATCH v3 2/4] perf: imx_perf: add support for i.MX95 platform
>=20
> i.MX95 has a DDR PMU which is almostly same as i.MX93, it now supports
> read beat and write beat filter capabilities. This will add support for
> i.MX95 and enhance the driver to support specific filter handling for it.
>=20
> Usage:
>=20
> For read beat:
> ~# perf stat -a -I 1000 -e
> imx9_ddr0/eddrtq_pm_rd_beat_filt2,counter=3D3,axi_mask=3DID_MASK,axi_id
> =3DID/
> ~# perf stat -a -I 1000 -e
> imx9_ddr0/eddrtq_pm_rd_beat_filt1,counter=3D4,axi_mask=3DID_MASK,axi_id
> =3DID/
> ~# perf stat -a -I 1000 -e
> imx9_ddr0/eddrtq_pm_rd_beat_filt0,counter=3D5,axi_mask=3DID_MASK,axi_id
> =3DID/
> eg: For edma2: perf stat -a -I 1000 -e
> imx9_ddr0/eddrtq_pm_rd_beat_filt0,counter=3D5,axi_mask=3D0x00f,axi_id=3D0=
x0
> 0c/
>=20
> For write beat:
> ~# perf stat -a -I 1000 -e
> imx9_ddr0/eddrtq_pm_wr_beat_filt,counter=3D2,axi_mask=3DID_MASK,axi_id=3D
> ID/
> eg: For edma2: perf stat -a -I 1000 -e
> imx9_ddr0/eddrtq_pm_wr_beat_filt,counter=3D2,axi_mask=3D0x00f,axi_id=3D0x=
00
> c/
>=20
> Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
>=20
> ---
> Changes in v2:
>  - put soc spefific axi filter events to drvdata according
>    to franks suggestions.
>  - adjust pmcfg axi_id and axi_mask config
> Changes in v3:
>  - no changes
> ---
>  drivers/perf/fsl_imx9_ddr_perf.c | 203 +++++++++++++++++++++++++-----
=20
I suggest you split this two patch. =20
1st patch rework imx93 only, which prepare for add imx95. All function is e=
qual.
2nd patch add imx95.=20

Frank
=20
> -
>  1 file changed, 169 insertions(+), 34 deletions(-)
>=20
> diff --git a/drivers/perf/fsl_imx9_ddr_perf.c
> b/drivers/perf/fsl_imx9_ddr_perf.c
> index 9685645bfe04..fd118773508d 100644
> --- a/drivers/perf/fsl_imx9_ddr_perf.c
> +++ b/drivers/perf/fsl_imx9_ddr_perf.c
> @@ -11,14 +11,24 @@
>  #include <linux/perf_event.h>
>=20
>  /* Performance monitor configuration */
> -#define PMCFG1  			0x00
> -#define PMCFG1_RD_TRANS_FILT_EN 	BIT(31)
> -#define PMCFG1_WR_TRANS_FILT_EN 	BIT(30)
> -#define PMCFG1_RD_BT_FILT_EN 		BIT(29)
> -#define PMCFG1_ID_MASK  		GENMASK(17, 0)
> +#define PMCFG1				0x00
> +#define MX93_PMCFG1_RD_TRANS_FILT_EN	BIT(31)
> +#define MX93_PMCFG1_WR_TRANS_FILT_EN	BIT(30)
> +#define MX93_PMCFG1_RD_BT_FILT_EN	BIT(29)
> +#define MX93_PMCFG1_ID_MASK		GENMASK(17, 0)
>=20
> -#define PMCFG2  			0x04
> -#define PMCFG2_ID			GENMASK(17, 0)
> +#define MX95_PMCFG1_WR_BEAT_FILT_EN	BIT(31)
> +#define MX95_PMCFG1_RD_BEAT_FILT_EN	BIT(30)
> +
> +#define PMCFG2				0x04
> +#define MX93_PMCFG2_ID			GENMASK(17, 0)
> +
> +#define PMCFG3				0x08
> +#define PMCFG4				0x0C
> +#define PMCFG5				0x10
> +#define PMCFG6				0x14
> +#define MX95_PMCFG_ID_MASK		GENMASK(9, 0)
> +#define MX95_PMCFG_ID			GENMASK(25, 16)
>=20
>  /* Global control register affects all counters and takes priority over =
local
> control registers */
>  #define PMGC0		0x40
> @@ -51,6 +61,7 @@ static DEFINE_IDA(ddr_ida);
>=20
>  struct imx_ddr_devtype_data {
>  	const char *identifier;		/* system PMU identifier for
> userspace */
> +	struct attribute **attrs;	/* AXI filter attributes */
>  };
>=20
>  struct ddr_pmu {
> @@ -67,16 +78,6 @@ struct ddr_pmu {
>  	int id;
>  };
>=20
> -static const struct imx_ddr_devtype_data imx93_devtype_data =3D {
> -	.identifier =3D "imx93",
> -};
> -
> -static const struct of_device_id imx_ddr_pmu_dt_ids[] =3D {
> -	{.compatible =3D "fsl,imx93-ddr-pmu", .data =3D &imx93_devtype_data},
> -	{ /* sentinel */ }
> -};
> -MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids);
> -
>  static ssize_t ddr_perf_identifier_show(struct device *dev,
>  					struct device_attribute *attr,
>  					char *page)
> @@ -178,7 +179,6 @@ static struct attribute *ddr_perf_events_attrs[] =3D =
{
>  	IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_6, 70),
>  	IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_7, 71),
>  	IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_empty, 72),
> -	IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, 73),
>=20
>  	/* counter3 specific events */
>  	IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_0, 64),
> @@ -190,7 +190,6 @@ static struct attribute *ddr_perf_events_attrs[] =3D =
{
>  	IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_6, 70),
>  	IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_7, 71),
>  	IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_full, 72),
> -	IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, 73),
>=20
>  	/* counter4 specific events */
>  	IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_0, 64),
> @@ -202,7 +201,6 @@ static struct attribute *ddr_perf_events_attrs[] =3D =
{
>  	IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_6, 70),
>  	IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_7, 71),
>  	IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2_rmw, 72),
> -	IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, 73),
>=20
>  	/* counter5 specific events */
>  	IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_0, 64),
> @@ -242,6 +240,28 @@ static const struct attribute_group
> ddr_perf_events_attr_group =3D {
>  	.attrs =3D ddr_perf_events_attrs,
>  };
>=20
> +static struct attribute *imx93_ddr_perf_events_attrs[] =3D {
> +	/* counter2 specific events */
> +	IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, 73),
> +	/* counter3 specific events */
> +	IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, 73),
> +	/* counter4 specific events */
> +	IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, 73),
> +	NULL,
> +};
> +
> +static struct attribute *imx95_ddr_perf_events_attrs[] =3D {
> +	/* counter2 specific events */
> +	IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_beat_filt, 73),
> +	/* counter3 specific events */
> +	IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt2, 73),
> +	/* counter4 specific events */
> +	IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt1, 73),
> +	/* counter5 specific events */
> +	IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt0, 73),
> +	NULL,
> +};
> +
>  PMU_FORMAT_ATTR(event, "config:0-7");
>  PMU_FORMAT_ATTR(counter, "config:8-15");
>  PMU_FORMAT_ATTR(axi_id, "config1:0-17");
> @@ -268,6 +288,28 @@ static const struct attribute_group *attr_groups[] =
=3D {
>  	NULL,
>  };
>=20
> +static const struct imx_ddr_devtype_data imx93_devtype_data =3D {
> +	.identifier =3D "imx93",
> +	.attrs =3D imx93_ddr_perf_events_attrs,
> +};
> +
> +static const struct imx_ddr_devtype_data imx95_devtype_data =3D {
> +	.identifier =3D "imx95",
> +	.attrs =3D imx95_ddr_perf_events_attrs,
> +};
> +
> +static const struct of_device_id imx_ddr_pmu_dt_ids[] =3D {
> +	{ .compatible =3D "fsl,imx93-ddr-pmu", .data =3D &imx93_devtype_data },
> +	{ .compatible =3D "fsl,imx95-ddr-pmu", .data =3D &imx95_devtype_data },
> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids);
> +
> +static inline bool is_imx93(struct ddr_pmu *pmu)
> +{
> +	return pmu->devtype_data =3D=3D &imx93_devtype_data;
> +}
> +
>  static void ddr_perf_clear_counter(struct ddr_pmu *pmu, int counter)
>  {
>  	if (counter =3D=3D CYCLES_COUNTER) {
> @@ -361,7 +403,7 @@ static void ddr_perf_counter_local_config(struct
> ddr_pmu *pmu, int config,
>  	}
>  }
>=20
> -static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cf=
g1,
> int cfg2)
> +static void imx93_ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg,
> int cfg1, int cfg2)
>  {
>  	u32 pmcfg1, pmcfg2;
>  	int event, counter;
> @@ -372,30 +414,80 @@ static void ddr_perf_monitor_config(struct
> ddr_pmu *pmu, int cfg, int cfg1, int
>  	pmcfg1 =3D readl_relaxed(pmu->base + PMCFG1);
>=20
>  	if (counter =3D=3D 2 && event =3D=3D 73)
> -		pmcfg1 |=3D PMCFG1_RD_TRANS_FILT_EN;
> +		pmcfg1 |=3D MX93_PMCFG1_RD_TRANS_FILT_EN;
>  	else if (counter =3D=3D 2 && event !=3D 73)
> -		pmcfg1 &=3D ~PMCFG1_RD_TRANS_FILT_EN;
> +		pmcfg1 &=3D ~MX93_PMCFG1_RD_TRANS_FILT_EN;
>=20
>  	if (counter =3D=3D 3 && event =3D=3D 73)
> -		pmcfg1 |=3D PMCFG1_WR_TRANS_FILT_EN;
> +		pmcfg1 |=3D MX93_PMCFG1_WR_TRANS_FILT_EN;
>  	else if (counter =3D=3D 3 && event !=3D 73)
> -		pmcfg1 &=3D ~PMCFG1_WR_TRANS_FILT_EN;
> +		pmcfg1 &=3D ~MX93_PMCFG1_WR_TRANS_FILT_EN;
>=20
>  	if (counter =3D=3D 4 && event =3D=3D 73)
> -		pmcfg1 |=3D PMCFG1_RD_BT_FILT_EN;
> +		pmcfg1 |=3D MX93_PMCFG1_RD_BT_FILT_EN;
>  	else if (counter =3D=3D 4 && event !=3D 73)
> -		pmcfg1 &=3D ~PMCFG1_RD_BT_FILT_EN;
> +		pmcfg1 &=3D ~MX93_PMCFG1_RD_BT_FILT_EN;
>=20
> -	pmcfg1 &=3D ~FIELD_PREP(PMCFG1_ID_MASK, 0x3FFFF);
> -	pmcfg1 |=3D FIELD_PREP(PMCFG1_ID_MASK, cfg2);
> +	pmcfg1 &=3D ~FIELD_PREP(MX93_PMCFG1_ID_MASK, 0x3FFFF);
> +	pmcfg1 |=3D FIELD_PREP(MX93_PMCFG1_ID_MASK, cfg2);
>  	writel(pmcfg1, pmu->base + PMCFG1);
>=20
>  	pmcfg2 =3D readl_relaxed(pmu->base + PMCFG2);
> -	pmcfg2 &=3D ~FIELD_PREP(PMCFG2_ID, 0x3FFFF);
> -	pmcfg2 |=3D FIELD_PREP(PMCFG2_ID, cfg1);
> +	pmcfg2 &=3D ~FIELD_PREP(MX93_PMCFG2_ID, 0x3FFFF);
> +	pmcfg2 |=3D FIELD_PREP(MX93_PMCFG2_ID, cfg1);
>  	writel(pmcfg2, pmu->base + PMCFG2);
>  }
>=20
> +static void imx95_ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg,
> int cfg1, int cfg2)
> +{
> +	u32 pmcfg1, pmcfg, offset =3D 0;
> +	int event, counter;
> +
> +	event =3D cfg & 0x000000FF;
> +	counter =3D (cfg & 0x0000FF00) >> 8;
> +
> +	pmcfg1 =3D readl_relaxed(pmu->base + PMCFG1);
> +
> +	if (counter =3D=3D 2 && event =3D=3D 73) {
> +		pmcfg1 |=3D MX95_PMCFG1_WR_BEAT_FILT_EN;
> +		offset =3D PMCFG3;
> +	} else if (counter =3D=3D 2 && event !=3D 73) {
> +		pmcfg1 &=3D ~MX95_PMCFG1_WR_BEAT_FILT_EN;
> +	}
> +
> +	if (counter =3D=3D 3 && event =3D=3D 73) {
> +		pmcfg1 |=3D MX95_PMCFG1_RD_BEAT_FILT_EN;
> +		offset =3D PMCFG4;
> +	} else if (counter =3D=3D 3 && event !=3D 73) {
> +		pmcfg1 &=3D ~MX95_PMCFG1_RD_BEAT_FILT_EN;
> +	}
> +
> +	if (counter =3D=3D 4 && event =3D=3D 73) {
> +		pmcfg1 |=3D MX95_PMCFG1_RD_BEAT_FILT_EN;
> +		offset =3D PMCFG5;
> +	} else if (counter =3D=3D 4 && event !=3D 73) {
> +		pmcfg1 &=3D ~MX95_PMCFG1_RD_BEAT_FILT_EN;
> +	}
> +
> +	if (counter =3D=3D 5 && event =3D=3D 73) {
> +		pmcfg1 |=3D MX95_PMCFG1_RD_BEAT_FILT_EN;
> +		offset =3D PMCFG6;
> +	} else if (counter =3D=3D 5 && event !=3D 73) {
> +		pmcfg1 &=3D ~MX95_PMCFG1_RD_BEAT_FILT_EN;
> +	}
> +
> +	writel(pmcfg1, pmu->base + PMCFG1);
> +
> +	if (offset) {
> +		pmcfg =3D readl_relaxed(pmu->base + offset);
> +		pmcfg &=3D ~(FIELD_PREP(MX95_PMCFG_ID_MASK, 0x3FF) |
> +				FIELD_PREP(MX95_PMCFG_ID, 0x3FF));
> +		pmcfg |=3D (FIELD_PREP(MX95_PMCFG_ID_MASK, cfg2) |
> +				FIELD_PREP(MX95_PMCFG_ID, cfg1));
> +		writel(pmcfg, pmu->base + offset);
> +	}
> +}
> +
>  static void ddr_perf_event_update(struct perf_event *event)
>  {
>  	struct ddr_pmu *pmu =3D to_ddr_pmu(event->pmu);
> @@ -476,12 +568,16 @@ static int ddr_perf_event_add(struct perf_event
> *event, int flags)
>  	hwc->idx =3D counter;
>  	hwc->state |=3D PERF_HES_STOPPED;
>=20
> +	if (is_imx93(pmu))
> +		/* read trans, write trans, read beat */
> +		imx93_ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2);
> +	else
> +		/* write beat, read beat2, read beat1, read beat */
> +		imx95_ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2);
> +
>  	if (flags & PERF_EF_START)
>  		ddr_perf_event_start(event, flags);
>=20
> -	/* read trans, write trans, read beat */
> -	ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2);
> -
>  	return 0;
>  }
>=20
> @@ -596,6 +692,39 @@ static int ddr_perf_offline_cpu(unsigned int cpu,
> struct hlist_node *node)
>  	return 0;
>  }
>=20
> +static int ddr_perf_add_events(struct ddr_pmu *pmu)
> +{
> +	int i, ret;
> +	struct attribute **attrs =3D pmu->devtype_data->attrs;
> +	struct device *pmu_dev =3D pmu->pmu.dev;
> +
> +	if (!attrs)
> +		return 0;
> +
> +	for (i =3D 0; attrs[i]; i++) {
> +		ret =3D sysfs_add_file_to_group(&pmu_dev->kobj, attrs[i],
> "events");
> +		if (ret) {
> +			dev_warn(pmu->dev, "i.MX9 DDR Perf add events
> failed (%d)\n", ret);
> +			return ret;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +static void ddr_perf_remove_events(struct ddr_pmu *pmu)
> +{
> +	int i;
> +	struct attribute **attrs =3D pmu->devtype_data->attrs;
> +	struct device *pmu_dev =3D pmu->pmu.dev;
> +
> +	if (!attrs)
> +		return;
> +
> +	for (i =3D 0; attrs[i]; i++)
> +		sysfs_remove_file_from_group(&pmu_dev->kobj, attrs[i],
> "events");
> +}
> +
>  static int ddr_perf_probe(struct platform_device *pdev)
>  {
>  	struct ddr_pmu *pmu;
> @@ -666,6 +795,10 @@ static int ddr_perf_probe(struct platform_device
> *pdev)
>  	if (ret)
>  		goto ddr_perf_err;
>=20
> +	ret =3D ddr_perf_add_events(pmu);
> +	if (ret)
> +		dev_warn(&pdev->dev, "i.MX9 DDR Perf filter events are
> missing\n");
> +
>  	return 0;
>=20
>  ddr_perf_err:
> @@ -683,6 +816,8 @@ static int ddr_perf_remove(struct platform_device
> *pdev)
>  {
>  	struct ddr_pmu *pmu =3D platform_get_drvdata(pdev);
>=20
> +	ddr_perf_remove_events(pmu);
> +
>  	cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu-
> >node);
>  	cpuhp_remove_multi_state(pmu->cpuhp_state);
>=20
> --
> 2.34.1