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Mon, 29 Jan 2024 22:50:41 -0600 Received: from [172.24.227.9] (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40U4ocXI093764; Mon, 29 Jan 2024 22:50:38 -0600 Message-ID: <792c972b-052e-4e24-a85f-9415fe02aa01@ti.com> Date: Tue, 30 Jan 2024 10:20:37 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird CC: , , , , , , , , , Subject: Re: [PATCH] PCI: j721e: Extend j721e_pcie_ctrl_init() for non syscon nodes Content-Language: en-US To: Andrew Davis References: <20240129104958.1139787-1-s-vadapalli@ti.com> <077682de-7789-4f1f-8dcc-aa47f4fb2dff@ti.com> From: Siddharth Vadapalli In-Reply-To: <077682de-7789-4f1f-8dcc-aa47f4fb2dff@ti.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Hello Andrew, On 29/01/24 20:49, Andrew Davis wrote: > On 1/29/24 4:49 AM, Siddharth Vadapalli wrote: .. >>       int ret; >>   -    syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-pcie-ctrl"); >> +    scm_conf = of_parse_phandle(node, "ti,syscon-pcie-ctrl", 0); >> +    if (!scm_conf) { >> +        dev_err(dev, "unable to get System Controller node\n"); >> +        return -ENODEV; >> +    } >> + >> +    syscon = device_node_to_regmap(scm_conf); > > Turning the entire "simple-bus" region into a regmap using this > function is just as broken as having it as a "syscon". The core > problem we are solving by getting rid of the blanket syscon nodes > is that it causes multiple mappings of the same register. This > can cause issues with regmap caching, read–modify–write, etc.. > > What you want to do is add a subnode to the simple-bus, have that > encapsulate just the registers used for PCIe, and have the PCIe > node point to that. Then this patch isn't needed. > > For an example, see how it's done for DSS[0]. Thank you for reviewing the patch. I will implement it similar to what's done for DSS as you pointed out. However, what about the existing SoCs which make use of the "ti,syscon-pcie-ctrl" property? Do you suggest that I add another device-tree property for pointing to the PCIE_CTRL register within the CTRL_MMR region, or do you suggest that I reuse the existing "ti,syscon-pcie-ctrl" property differently in the SoCs like J784S4 where the scm_conf node is a "simple-bus"? The "ti,syscon-pcie-ctrl" property as defined in the device-tree bindings has two elements with the first being the phandle to the scm_conf node and the second being the offset of the PCIE_CTRL register. The newer implementation you are suggesting will either require a new property which accepts only one element namely the phandle to the node within scm_conf corresponding to the PCIE_CTRL register. Will adding a new property be acceptable? .. -- Regards, Siddharth.