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Date: Tue, 30 Jan 2024 09:03:43 +0200
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Subject: Re: [PATCH v2] mmc: renesas_sdhi: Fix change point of data handling
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To: Wolfram Sang <wsa+renesas@sang-engineering.com>, ulf.hansson@linaro.org,
 takeshi.saito.xv@renesas.com, masaharu.hayakawa.ry@renesas.com,
 yoshihiro.shimoda.uh@renesas.com, linux-mmc@vger.kernel.org,
 linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org,
 Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
References: <20240117110646.1317843-1-claudiu.beznea.uj@bp.renesas.com>
 <ZbeEPg1jc5qWJa5m@ninjato>
From: claudiu beznea <claudiu.beznea@tuxon.dev>
In-Reply-To: <ZbeEPg1jc5qWJa5m@ninjato>
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Hi, Wolfram,

On 29.01.2024 12:55, Wolfram Sang wrote:
> Hi Claudiu,
> 
> but one thing I can ask already:
> 
>> Investigating it on RZ/G3S lead to the conclusion that every time the issue
>> is reproduced all the probed TAPs are OK. According to datasheet, when this
>> happens the change point of data need to be considered for tuning.
> 
> Yes, "considered" means here it should be *avoided*.

My understanding was the other way around from this statement found in
RZ/G3S hw manual:

"If all of the TAP [i] is OK, the sampling clock position is selected by
identifying the change point of data.
 Change point of the data can be found in the value of SCC_SMPCMP register.
Usage example is Section 33.8.3, Change
 point of the input data."

> 
>> Previous code considered the change point of data happens when the content
>> of the SMPCMP register is zero. According to RZ/V2M hardware manual,
> 
> When SMPCMP is zero, there is *no* change point. Which is good.

That was my understanding, too.

> 
>> chapter "Change Point of the Input Data" (as this is the most clear
>> description that I've found about change point of the input data and all
>> RZ hardware manual are similar on this chapter),
> 
> I also have a chapter named like this. If you check the diagram, change
> point is between TAP2 and 3, so the suggested TAP to use is 6 or 7. As
> far away as possible from the change point.

My understanding was different here as of the following hw manual statement:

"As the width of the input data is 1 (UI), select TAP6 or TAP7 which is

*the median* of next TAP3 from TAP3"

I understand from this that the median value should be considered here.

> 
>> at the time of tuning,
>> data is captured by the previous and next TAPs and the result is stored in
>> the SMPCMP register (previous TAP in bits 22..16, next TAP in bits 7..0).
>> If there is a mismatch b/w the previous and the next TAPs, it indicates
>> that there is a change point of the input data.
> 
> This is correct.
> 
>> To comply with this, the code checks if this mismatch is present and
>> updates the priv->smpcmp mask.
> 
> That means you select the "change point" instead of avoiding it?
> 
>> This change has been checked on the devices with the following DTSes by
>> doing 50 consecutive reboots and checking for the tuning failure message:
> 
> Okay, you might not have a failure message, but you might have selected
> the worst TAP. Or?
> 
>> +			if (cmpngu_data != cmpngd_data)
>> +				set_bit(i, priv->smpcmp);
> 
> Really looks like you select the change point instead of avoiding it.

Looking again at it and digesting what you said about the tuning here, yes
it seems I did it this way.

> 
> However, with some SD cards, I also see the EIO error you see. So, there
> might be room to improve TAP selection when all TAPs are good. I need to
> check if this is really is the same case for the SD cards in question.

Maybe better would be to change this condition:

			if (cmpngu_data != cmpngd_data)
				set_bit(i, priv->smpcmp);

like this:
			if (cmpngu_data == cmpngd_data)
				set_bit(i, priv->smpcmp);

?

I need to check it, though.

Thanks for your input,
Claudiu Beznea

> 
> Happy hacking,
> 
>    Wolfram
>