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Tue, 30 Jan 2024 02:00:57 -0800 (PST) Received: from mobilestation ([178.176.56.174]) by smtp.gmail.com with ESMTPSA id y8-20020ac24208000000b0051010608804sm1390457lfh.65.2024.01.30.02.00.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jan 2024 02:00:56 -0800 (PST) Date: Tue, 30 Jan 2024 13:00:53 +0300 From: Serge Semin To: Mrinmay Sarkar Cc: vkoul@kernel.org, jingoohan1@gmail.com, conor+dt@kernel.org, konrad.dybcio@linaro.org, manivannan.sadhasivam@linaro.org, robh+dt@kernel.org, quic_shazhuss@quicinc.com, quic_nitegupt@quicinc.com, quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com, dmitry.baryshkov@linaro.org, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, quic_parass@quicinc.com, quic_schintav@quicinc.com, quic_shijjose@quicinc.com, Gustavo Pimentel , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Kishon Vijay Abraham I , dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, mhi@lists.linux.dev Subject: Re: [PATCH v1 0/6] Add Change to integrate HDMA with dwc ep driver Message-ID: References: <1705669223-5655-1-git-send-email-quic_msarkar@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1705669223-5655-1-git-send-email-quic_msarkar@quicinc.com> Hi Mrinmay On Fri, Jan 19, 2024 at 06:30:16PM +0530, Mrinmay Sarkar wrote: > Hyper DMA (HDMA) is already supported by the dw-edma dmaengine driver. > Unlike it's predecessor Embedded DMA (eDMA), HDMA supports only the > unrolled mapping format. This patch series is to integrate HDMA with > dwc ep driver. > > Add change to provide a valid base address of the CSRs from the > platform driver and also provides read/write channels count from > platform driver since there is no standard way to auto detect the > number of available read/write channels in a platform and set the > mapping format in platform driver for HDMA. > > This series passes 'struct dw_edma_chip' to irq_vector() as it needs > to access that particular structure and fix to get the eDMA/HDMA > max channel count. Also move the HDMA max channel definition to edma.h > to maintain uniformity with eDMA. Thanks for the patchset. I'll have a look at it later on this week or early on the next one. If you wish you can resubmit it by then with the Dmitry' and Mani' notes fixed. -Serge(y) > > Dependency > ---------- > Depends on: > https://lore.kernel.org/dmaengine/20231117-b4-feature_hdma_mainline-v6-0-ebf7aa0e40d7@bootlin.com/ > https://lore.kernel.org/all/1701432377-16899-1-git-send-email-quic_msarkar@quicinc.com/ > > Manivannan Sadhasivam (4): > dmaengine: dw-edma: Pass 'struct dw_edma_chip' to irq_vector() > dmaengine: dw-edma: Introduce helpers for getting the eDMA/HDMA max > channel count > PCI: dwc: Add HDMA support > dmaengine: dw-edma: Move HDMA_V0_MAX_NR_CH definition to edma.h > > Mrinmay Sarkar (2): > PCI: qcom-ep: Provide number of read/write channel for HDMA > PCI: epf-mhi: Add flag to enable HDMA for SA8775P > > drivers/dma/dw-edma/dw-edma-core.c | 29 ++++++++++--- > drivers/dma/dw-edma/dw-edma-pcie.c | 4 +- > drivers/dma/dw-edma/dw-hdma-v0-core.c | 4 +- > drivers/dma/dw-edma/dw-hdma-v0-regs.h | 3 +- > drivers/pci/controller/dwc/pcie-designware.c | 63 ++++++++++++++++++++++------ > drivers/pci/controller/dwc/pcie-qcom-ep.c | 19 ++++++++- > drivers/pci/endpoint/functions/pci-epf-mhi.c | 1 + > include/linux/dma/edma.h | 18 +++++++- > 8 files changed, 115 insertions(+), 26 deletions(-) > > -- > 2.7.4 >