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From: Geert Uytterhoeven <geert@linux-m68k.org>
Date: Tue, 30 Jan 2024 11:35:46 +0100
Message-ID: <CAMuHMdWbPooCMqyKjTh+uJgAqh=az0+DOQAJYKQ7cuBrxyV1-w@mail.gmail.com>
Subject: Re: [PATCH v6 1/4] pinctrl: renesas: rzg2l: Improve code for readability
To: Prabhakar <prabhakar.csengg@gmail.com>
Cc: Magnus Damm <magnus.damm@gmail.com>, Linus Walleij <linus.walleij@linaro.org>, 
	Rob Herring <robh+dt@kernel.org>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, 
	linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, 
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, 
	linux-gpio@vger.kernel.org, Biju Das <biju.das.jz@bp.renesas.com>, 
	Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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Hi Prabhakar,

On Mon, Jan 29, 2024 at 2:56=E2=80=AFPM Prabhakar <prabhakar.csengg@gmail.c=
om> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> As the RZ/G2L pinctrl driver is extensively utilized by numerous SoCs and
> has experienced substantial growth, enhance code readability by
> incorporating FIELD_PREP_CONST/FIELD_GET macros wherever necessary.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-pinctrl for v6.9.

> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c

> @@ -90,14 +93,18 @@
>   * (b * 8) and f is the pin configuration capabilities supported.
>   */
>  #define RZG2L_SINGLE_PIN               BIT(31)
> +#define RZG2L_SINGLE_PIN_INDEX_MASK    GENMASK(30, 24)
> +#define RZG2L_SINGLE_PIN_BITS_MASK     GENMASK(22, 20)
> +
>  #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \
> -                                        ((p) << 24) | ((b) << 20) | (f))
> -#define RZG2L_SINGLE_PIN_GET_BIT(x)    (((x) & GENMASK(22, 20)) >> 20)
> +                                        FIELD_PREP_CONST(RZG2L_SINGLE_PI=
N_INDEX_MASK, (p)) | \
> +                                        FIELD_PREP_CONST(RZG2L_SINGLE_PI=
N_BITS_MASK, (b)) | \
> +                                        FIELD_PREP_CONST(PIN_CFG_MASK, (=
f)))
>
> -#define RZG2L_PIN_CFG_TO_CAPS(cfg)             ((cfg) & GENMASK(19, 0))
> +#define RZG2L_PIN_CFG_TO_CAPS(cfg)             ((cfg) & PIN_CFG_MASK)

Do you mind if I drop RZG2L_PIN_CFG_TO_CAPS() and replace its two
users by FIELD_GET(PIN_CFG_MASK, *pin_data) while applying?

>  #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg)      ((cfg) & RZG2L_SINGLE_PIN=
 ? \
> -                                               (((cfg) & GENMASK(30, 24)=
) >> 24) : \
> -                                               (((cfg) & GENMASK(26, 20)=
) >> 20))
> +                                                FIELD_GET(RZG2L_SINGLE_P=
IN_INDEX_MASK, (cfg)) : \
> +                                                FIELD_GET(PIN_CFG_PIN_RE=
G_MASK, (cfg)))
>
>  #define P(off)                 (0x0000 + (off))
>  #define PM(off)                        (0x0100 + (off) * 2)

Gr{oetje,eeting}s,

                        Geert

--=20
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k=
org

In personal conversations with technical people, I call myself a hacker. Bu=
t
when I'm talking to journalists I just say "programmer" or something like t=
hat.
                                -- Linus Torvalds