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Message-ID: <32669bc7-90b5-48d9-8845-2e072a477c6e@linaro.org>
Date: Tue, 30 Jan 2024 17:05:06 +0100
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Subject: Re: [PATCH 2/3] dt-bindings: fpga: xlnx,fpga-slave-selectmap: add DT
 schema
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To: Charles Perry <charles.perry@savoirfairelinux.com>
Cc: mdf@kernel.org, hao wu <hao.wu@intel.com>, yilun xu <yilun.xu@intel.com>,
 trix@redhat.com, krzysztof kozlowski+dt <krzysztof.kozlowski+dt@linaro.org>,
 Brian CODY <bcody@markem-imaje.com>,
 Allen VANDIVER <avandiver@markem-imaje.com>, linux-fpga@vger.kernel.org,
 devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
References: <20240129225602.3832449-1-charles.perry@savoirfairelinux.com>
 <20240129225602.3832449-2-charles.perry@savoirfairelinux.com>
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From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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On 30/01/2024 16:45, Charles Perry wrote:
> 
>>> +
>>> +  reg:
>>> +    description:
>>> +      At least 1 byte of memory mapped IO
>>> +    maxItems: 1
>>> +
>>> +  prog_b-gpios:
>>
>>
>> No underscores in names.
>>
> 
> This is heavily based on "xlnx,fpga-slave-serial.yaml" which uses an underscore.
> I can use a dash instead but that would make things inconsistent across the two schemas. 

Inconsistency is not a problem. Duplicating technical debt is.

> 
>>
>>> +    description:
>>> +      config pin (referred to as PROGRAM_B in the manual)
>>> +    maxItems: 1
>>> +
>>> +  done-gpios:
>>> +    description:
>>> +      config status pin (referred to as DONE in the manual)
>>> +    maxItems: 1
>>> +
>>> +  init-b-gpios:
>>
>> Is there init-a? Open other bindings and look how these are called there.
>>
> 
> No, the "-b" is there to denote that the signal is active low. I think its shorthand
> for "bar" which is the overline (‾) that electronic engineer put on top of the name of the
> signal on schematics. It comes from the datasheet.

Then just "init-gpios"

..

>>> +required:
>>> +  - compatible
>>> +  - reg
>>> +  - prog_b-gpios
>>> +  - done-gpios
>>> +  - init-b-gpios
>>> +
>>> +additionalProperties: true
>>
>> Nope, this cannot bue true.
>>
> 
> Ok, I'll put this to false but I'm not quite sure I understand the implications.
> 
> My reasoning behind assigning this to true was that the FPGA is an external
> device on a bus that needs to be configured by a bus controller. The bus controller
> would be the parent of the fpga DT node and the later would contain properties
> parsed by the bus controller driver.

Which bus controller? MMIO bus does not parse children properties.
Anyway, if that's the case you miss $ref to respective
peripheral-props.yaml matching your bus and then "unevaluatedProperties:
false".

Best regards,
Krzysztof