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From: Vinod Koul <vkoul@kernel.org>
To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, 
 kishon@kernel.org, Qiang Yu <quic_qianyu@quicinc.com>
Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, 
 linux-kernel@vger.kernel.org, quic_cang@quicinc.com, quic_mrana@quicinc.com
In-Reply-To: <1703742157-69840-1-git-send-email-quic_qianyu@quicinc.com>
References: <1703742157-69840-1-git-send-email-quic_qianyu@quicinc.com>
Subject: Re: [PATCH 0/2] phy: qcom: qmp-pcie: Update PCIe PHY settings for
 SM8550
Message-Id: <170663638451.685888.12123923812372214913.b4-ty@kernel.org>
Date: Tue, 30 Jan 2024 23:09:44 +0530
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On Thu, 28 Dec 2023 13:42:35 +0800, Qiang Yu wrote:
> Align PCIe0/PCIe1 PHY settings with SM8550 latest PCIe PHY Hardware
> Programming Guide.
> 
> Can Guo (1):
>   phy: qcom: qmp-pcie: Update PCIe1 PHY settings for SM8550
> 
> Qiang Yu (1):
>   phy: qcom: qmp-pcie: Update PCIe0 PHY settings for SM8550
> 
> [...]

Applied, thanks!

[1/2] phy: qcom: qmp-pcie: Update PCIe1 PHY settings for SM8550
      commit: 06e34728827cb47026e80db22304d03ee83c73a8
[2/2] phy: qcom: qmp-pcie: Update PCIe0 PHY settings for SM8550
      commit: 80082fc89edde66fe61ab85d23ea27b245fe73cb

Best regards,
-- 
~Vinod