Received-SPF: pass (google.com: domain of linux-kernel+bounces-45543-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) client-ip=2604:1380:4601:e00::3;
From: Frank Li <Frank.Li@nxp.com>
Date: Tue, 30 Jan 2024 19:45:28 -0500
Subject: [PATCH 3/6] PCI: dwc: Add outbound MSG TLPs support
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: 7bit
Message-Id: <20240130-pme_msg-v1-3-d52b0add5c7c@nxp.com>
References: <20240130-pme_msg-v1-0-d52b0add5c7c@nxp.com>
In-Reply-To: <20240130-pme_msg-v1-0-d52b0add5c7c@nxp.com>
To: Bjorn Helgaas <bhelgaas@google.com>, Jingoo Han <jingoohan1@gmail.com>, 
 Gustavo Pimentel <gustavo.pimentel@synopsys.com>, 
 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>, 
 Lorenzo Pieralisi <lpieralisi@kernel.org>, 
 =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= <kw@linux.com>, 
 Rob Herring <robh@kernel.org>, 
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, 
 Conor Dooley <conor+dt@kernel.org>, imx@lists.linux.dev
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, 
 devicetree@vger.kernel.org, Frank Li <Frank.Li@nxp.com>, 
 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>, 
 Serge Semin <fancer.lancer@gmail.com>
Precedence: bulk
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0:
	=?utf-8?B?OW8yYUFxTlg2S2hwSlFhVWZZOUR5SUxQWTZyUFY1aWlRQUxwbUlqUndlc3g4?=
 =?utf-8?B?V2tmUHlvM0RZdFdwcHg0cEh3a1p4Wnh5bWtIaS90WU1wMkJLT0VTRk1FWlJs?=
 =?utf-8?B?dDhuaHVxYWpEY3kyRVN1S0ZsQ3RGTnBqVkhObjdnY09aV1JadnlWQW9UUEh5?=
 =?utf-8?B?S2VabDlRczVSZXU2WkR1VEhKUDZXdTh6K0RQWkZRK3RXMlZFSktVdUhOVVF6?=
 =?utf-8?B?SXpaeWFsK3VYcENrZ3dyR2I4cG5FaHl1TGJVc1dDMVlUM3lkS2ZsdkdMQkh0?=
 =?utf-8?B?M2tPUjhEYVNrV1hKaWZDOW9MQmVObk41Vk9NNXRnaFVnc3RuR1A2SXNkSjVr?=
 =?utf-8?B?ZHltZWw2NVVic3hXSVlsM280VzQvK2FweFdXcWpoWlFYTEY3OW5CZkdCdi9Y?=
 =?utf-8?B?S0lLYndTTDVuVm1CeElFcE1qM2wzMWh4ank2TEZUNUxCSUlYSFR6YSt6ZUY3?=
 =?utf-8?B?WVgyV0pMUnRLd1pTeXFudTRoRzZITnMvVWpvd3dlRngyeEF0VHlZd0ZaS0JE?=
 =?utf-8?B?NS9ybVFGSDRQekI1UG13UGhuRG9IbUx3QlRPWjJwN1NaZzNTUmY0V2VXbWhM?=
 =?utf-8?B?ck9OUDhNQktoYVBzdmw1cjlFakFVOVBrL09xdXlCbjJaWUdoSGZpUll4SG9y?=
 =?utf-8?B?NmZLQmNVQ3VkMmR2dzZSRFROTmpXS3V5aHdhcWRpUlhQVTU0UThRdzEvUWFm?=
 =?utf-8?B?MUZkRWRVdjA4V1VtYVN4V1FGaE52TkhiUEhtZm9OVkFMMnlNOVdhOGtaUEZ4?=
 =?utf-8?B?WUgzTUcrcGpDQ1ZuTlpPdUZXSllVWWh0czRscjhmRDVwVkkwajlqeElCd2do?=
 =?utf-8?B?dURXS1djcVJBK2UwWGNMR3EyL1Njek9zWkZhSzljdWVrT3pWVFNDUlhBNWdw?=
 =?utf-8?B?bElQSk5LU1J4d0VoeUVJTjg0bjlNVUtSQmdaZENid1kyTFBpSnBZL2dVRFRk?=
 =?utf-8?B?Y3k0MUZwQWdkckFzQ3hSaWlOc2d5SWpBSmVXZ0g2Um83blRlMTJ4Yk51TmNV?=
 =?utf-8?B?amhtWEc4ODErdThiMkxGdExBNDdpRDMrc3BLaHdwenpDVi9EaWZGN1FSTUVl?=
 =?utf-8?B?RTVhaHdtbUdBL0pVeGx3UGJ5eGZVUmsraTdCNmxaNjJuengwcm96R09aeFBy?=
 =?utf-8?B?MG5pMm1wbk9abnRaV29KLzdxSURqWjZ6RDl1WGlybXp6NFJXeldjcnR4MHZQ?=
 =?utf-8?B?aWtHS0pwY3ZCRXhqMzlGNGhDTEltS3JtM1Q0T2k4NVpjdEpzdWxXWGRBMXhG?=
 =?utf-8?B?MWk1a3BNQU1oY1podGd0UEJsS0RUa1BUWVVSZW83ZEVhYzZlbE9KR21qM0ky?=
 =?utf-8?B?ZGhsbkpObXV2UG1vM3dEY3ZmR2QyVVBIWFNWQ0FwZXZGMWhYTk1nYjBMNmU3?=
 =?utf-8?B?clU5STdXazZ0Y2NJYVpSZlBwdDcyKzlneHl4Um5LZ1BKcXRBczRsOTBXMHhs?=
 =?utf-8?B?VWtKY1FDQ1lnenZsU2JURTFMdER6UmYyejJ6Nkg3OUkvWnJNaFNHWW5KaW1C?=
 =?utf-8?B?M2VOWjlkdFdWR1U5YTF1R3ZGVC9KQ1BoSklkbi9ZN2VqZ05BL2JYMUpIYjF5?=
 =?utf-8?B?czYrT1RvR0NFSG9IV2QrWGRFUmNFT0w2VklTT3FFMU1reUlNZTE4RjNxZlFT?=
 =?utf-8?B?SW5JckUzSlpBYlcyNGtjbm5DaW1xajV2RWh6RE94b2NPQlkxMnk0K2M1ZzFu?=
 =?utf-8?B?NUdxNWE2bFIwRWRuL0crUUM5TGxURGQ5cDAvd3RwVW1TYm5kVjRHOVBZZHFC?=
 =?utf-8?B?bVRlbGhSWWRTSktGSEZZQmNDS3B1dU5lNFBSR1E0eHpSYjJiTTZEZWJHNTZY?=
 =?utf-8?B?WStOM0F3dXJ1TlZrUjNmKzlnTnRTR2N6b29qc25UTVhuNXIzZjdMWEFPMlNC?=
 =?utf-8?B?anJZNEhiaXFSbDNlYTRXVDMzNVQ4Y3E5K2w1MHp3cDdpd1dqZzZIYncySVZL?=
 =?utf-8?B?MS9CeXl6VktIWm5xUmp3c3VpbHU5YXRUay9lN2x5RThuWTUzbEhFWWRjQlFR?=
 =?utf-8?B?aWtaTWNaVkttZUJhSHdyNXBhYjMxV1o4cTFvdldUbXpQdXNFSng1VnR5YkFp?=
 =?utf-8?B?UkIrQjZrait4NHQzb0lGbENXR3d0YVU4VU9YRW5QWVFrNGgwK1Jxa0JQNE84?=
 =?utf-8?Q?LpQLoCeYFgGCntgwbrTNZcwSP?=
X-OriginatorOrg: nxp.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 32d440c3-e25a-4898-aeda-08dc21f601b7
X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Jan 2024 00:46:05.5321
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: cCLUSoEvzbp5jd2rR+XZc90H4gwloETCb7YpocwdyKSpYwtnzNLP+oMxAN32oSrRHq2dCiNOWmrgDaI87VvgTg==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB6877

From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Add "code" and "routing" into struct dw_pcie_ob_atu_cfg for triggering
INTx IRQs by iATU in the PCIe endpoint mode in near the future.
PCIE_ATU_INHIBIT_PAYLOAD is set to issue TLP type of Msg instead of
MsgD. So, this implementation supports the data-less messages only
for now.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 drivers/pci/controller/dwc/pcie-designware.c | 9 +++++++--
 drivers/pci/controller/dwc/pcie-designware.h | 4 ++++
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index df2575ec5f44c..ba909fade9db1 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -499,7 +499,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
 	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET,
 			      upper_32_bits(atu->pci_addr));
 
-	val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no);
+	val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no);
 	if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) &&
 	    dw_pcie_ver_is_ge(pci, 460A))
 		val |= PCIE_ATU_INCREASE_REGION_SIZE;
@@ -507,7 +507,12 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
 		val = dw_pcie_enable_ecrc(val);
 	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
 
-	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE);
+	val = PCIE_ATU_ENABLE;
+	if (atu->type == PCIE_ATU_TYPE_MSG) {
+		/* The data-less messages only for now */
+		val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code;
+	}
+	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val);
 
 	/*
 	 * Make sure ATU enable takes effect before any subsequent config
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index d21db82e586d5..703b50bc5e0f1 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -148,11 +148,13 @@
 #define PCIE_ATU_TYPE_IO		0x2
 #define PCIE_ATU_TYPE_CFG0		0x4
 #define PCIE_ATU_TYPE_CFG1		0x5
+#define PCIE_ATU_TYPE_MSG		0x10
 #define PCIE_ATU_TD			BIT(8)
 #define PCIE_ATU_FUNC_NUM(pf)           ((pf) << 20)
 #define PCIE_ATU_REGION_CTRL2		0x004
 #define PCIE_ATU_ENABLE			BIT(31)
 #define PCIE_ATU_BAR_MODE_ENABLE	BIT(30)
+#define PCIE_ATU_INHIBIT_PAYLOAD	BIT(22)
 #define PCIE_ATU_FUNC_NUM_MATCH_EN      BIT(19)
 #define PCIE_ATU_LOWER_BASE		0x008
 #define PCIE_ATU_UPPER_BASE		0x00C
@@ -303,6 +305,8 @@ struct dw_pcie_ob_atu_cfg {
 	int index;
 	int type;
 	u8 func_no;
+	u8 code;
+	u8 routing;
 	u64 cpu_addr;
 	u64 pci_addr;
 	u64 size;

-- 
2.34.1