Received-SPF: pass (google.com: domain of linux-kernel+bounces-45754-linux.lists.archive=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99;
From: "Alim Akhtar" <alim.akhtar@samsung.com>
To: "'Shradha Todi'" <shradha.t@samsung.com>, <linux-clk@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>, <linux-samsung-soc@vger.kernel.org>
Cc: <mturquette@baylibre.com>, <sboyd@kernel.org>, <jingoohan1@gmail.com>,
	<lpieralisi@kernel.org>, <kw@linux.com>, <robh@kernel.org>,
	<bhelgaas@google.com>, <krzysztof.kozlowski@linaro.org>,
	<linux@armlinux.org.uk>, <m.szyprowski@samsung.com>,
	<manivannan.sadhasivam@linaro.org>, <pankaj.dubey@samsung.com>
In-Reply-To: <20240124103838.32478-3-shradha.t@samsung.com>
Subject: RE: [PATCH v4 2/2] PCI: exynos: Adapt to clk_bulk_* APIs
Date: Wed, 31 Jan 2024 10:35:10 +0530
Message-ID: <009c01da5403$12b926d0$382b7470$@samsung.com>
Precedence: bulk
MIME-Version: 1.0
Content-Transfer-Encoding: quoted-printable
Thread-Index: AQIcpPks/WB953w72Rl3v8cfkz9jJgIOwv9MAllxpn6wS3ptMA==
Content-Language: en-us
Content-Type: text/plain; charset="utf-8"
CMS-TYPE: 105P
DLP-Filter: Pass
References: <20240124103838.32478-1-shradha.t@samsung.com>
	<CGME20240124103858epcas5p3d96cdbe8a6c8f31ccc934025411a09b8@epcas5p3.samsung.com>
	<20240124103838.32478-3-shradha.t@samsung.com>

Hello Shradha

> -----Original Message-----
> From: Shradha Todi <shradha.t=40samsung.com>
> Sent: Wednesday, January 24, 2024 4:09 PM
> To: linux-clk=40vger.kernel.org; linux-kernel=40vger.kernel.org; linux-
> pci=40vger.kernel.org; linux-arm-kernel=40lists.infradead.org; linux-sams=
ung-
> soc=40vger.kernel.org
> Cc: mturquette=40baylibre.com; sboyd=40kernel.org; jingoohan1=40gmail.com=
;
> lpieralisi=40kernel.org; kw=40linux.com; robh=40kernel.org;
> bhelgaas=40google.com; krzysztof.kozlowski=40linaro.org;
> alim.akhtar=40samsung.com; linux=40armlinux.org.uk;
> m.szyprowski=40samsung.com; manivannan.sadhasivam=40linaro.org;
> pankaj.dubey=40samsung.com; Shradha Todi <shradha.t=40samsung.com>
> Subject: =5BPATCH v4 2/2=5D PCI: exynos: Adapt to clk_bulk_* APIs
>=20
> There is no need to hardcode the clock info in the driver as driver can r=
ely on
> the devicetree to supply the clocks required for the functioning of the
> peripheral. Get rid of the static clock info and obtain the platform supp=
lied
> clocks. All the clocks supplied is obtained and enabled using the
> devm_clk_bulk_get_all_enable() API.
>=20
> Signed-off-by: Shradha Todi <shradha.t=40samsung.com>
> ---
Reviewed-by: Alim Akhtar <alim.akhtar=40samsung.com>

>  drivers/pci/controller/dwc/pci-exynos.c =7C 54 ++-----------------------
>  1 file changed, 4 insertions(+), 50 deletions(-)
>=20
> diff --git a/drivers/pci/controller/dwc/pci-exynos.c
> b/drivers/pci/controller/dwc/pci-exynos.c
> index ec5611005566..3234eb5be1fb 100644
> --- a/drivers/pci/controller/dwc/pci-exynos.c
> +++ b/drivers/pci/controller/dwc/pci-exynos.c
> =40=40 -54,43 +54,11 =40=40
>  struct exynos_pcie =7B
>  	struct dw_pcie			pci;
>  	void __iomem			*elbi_base;
> -	struct clk			*clk;
> -	struct clk			*bus_clk;
> +	struct clk_bulk_data		*clks;
>  	struct phy			*phy;
>  	struct regulator_bulk_data	supplies=5B2=5D;
>  =7D;
>=20
> -static int exynos_pcie_init_clk_resources(struct exynos_pcie *ep) -=7B
> -	struct device *dev =3D ep->pci.dev;
> -	int ret;
> -
> -	ret =3D clk_prepare_enable(ep->clk);
> -	if (ret) =7B
> -		dev_err(dev, =22cannot enable pcie rc clock=22);
> -		return ret;
> -	=7D
> -
> -	ret =3D clk_prepare_enable(ep->bus_clk);
> -	if (ret) =7B
> -		dev_err(dev, =22cannot enable pcie bus clock=22);
> -		goto err_bus_clk;
> -	=7D
> -
> -	return 0;
> -
> -err_bus_clk:
> -	clk_disable_unprepare(ep->clk);
> -
> -	return ret;
> -=7D
> -
> -static void exynos_pcie_deinit_clk_resources(struct exynos_pcie *ep) -=
=7B
> -	clk_disable_unprepare(ep->bus_clk);
> -	clk_disable_unprepare(ep->clk);
> -=7D
> -
>  static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg)  =
=7B
>  	writel(val, base + reg);
> =40=40 -332,17 +300,9 =40=40 static int exynos_pcie_probe(struct platform=
_device
> *pdev)
>  	if (IS_ERR(ep->elbi_base))
>  		return PTR_ERR(ep->elbi_base);
>=20
> -	ep->clk =3D devm_clk_get(dev, =22pcie=22);
> -	if (IS_ERR(ep->clk)) =7B
> -		dev_err(dev, =22Failed to get pcie rc clock=5Cn=22);
> -		return PTR_ERR(ep->clk);
> -	=7D
> -
> -	ep->bus_clk =3D devm_clk_get(dev, =22pcie_bus=22);
> -	if (IS_ERR(ep->bus_clk)) =7B
> -		dev_err(dev, =22Failed to get pcie bus clock=5Cn=22);
> -		return PTR_ERR(ep->bus_clk);
> -	=7D
> +	ret =3D devm_clk_bulk_get_all_enable(dev, &ep->clks);
> +	if (ret < 0)
> +		return ret;
>=20
>  	ep->supplies=5B0=5D.supply =3D =22vdd18=22;
>  	ep->supplies=5B1=5D.supply =3D =22vdd10=22;
> =40=40 -351,10 +311,6 =40=40 static int exynos_pcie_probe(struct platform=
_device
> *pdev)
>  	if (ret)
>  		return ret;
>=20
> -	ret =3D exynos_pcie_init_clk_resources(ep);
> -	if (ret)
> -		return ret;
> -
>  	ret =3D regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep-
> >supplies);
>  	if (ret)
>  		return ret;
> =40=40 -369,7 +325,6 =40=40 static int exynos_pcie_probe(struct platform_=
device
> *pdev)
>=20
>  fail_probe:
>  	phy_exit(ep->phy);
> -	exynos_pcie_deinit_clk_resources(ep);
>  	regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies);
>=20
>  	return ret;
> =40=40 -383,7 +338,6 =40=40 static int __exit exynos_pcie_remove(struct
> platform_device *pdev)
>  	exynos_pcie_assert_core_reset(ep);
>  	phy_power_off(ep->phy);
>  	phy_exit(ep->phy);
> -	exynos_pcie_deinit_clk_resources(ep);
>  	regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies);
>=20
>  	return 0;
> --
> 2.17.1