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b=plI84fsvQdZCIor28qBhJhybrZOCubuzNVqmVGVgsuBrOOK4jWCms72LkGtYDkEUDCdrsa8RWxFswDFUy7wqjBefetTyj6rZKb5TC0cDGWs5lPWDw3QVze+JX9cnedFRaNxQwpuniNtiLtu0T33Y3D03NeuvovXIAvG0Ptwktlg= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from DU2PR04MB8822.eurprd04.prod.outlook.com (2603:10a6:10:2e1::11) by DU2PR04MB8917.eurprd04.prod.outlook.com (2603:10a6:10:2e0::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7249.24; Wed, 31 Jan 2024 05:51:52 +0000 Received: from DU2PR04MB8822.eurprd04.prod.outlook.com ([fe80::d45f:4483:c11:68b0]) by DU2PR04MB8822.eurprd04.prod.outlook.com ([fe80::d45f:4483:c11:68b0%7]) with mapi id 15.20.7228.029; Wed, 31 Jan 2024 05:51:52 +0000 From: Xu Yang To: Frank.li@nxp.com, will@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, john.g.garry@oracle.com, jolsa@kernel.org, namhyung@kernel.org, irogers@google.com Cc: linux-imx@nxp.com, mike.leach@linaro.org, leo.yan@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, alexander.shishkin@linux.intel.com, adrian.hunter@intel.com, xu.yang_2@nxp.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, imx@lists.linux.dev Subject: [PATCH v4 2/6] perf: imx_perf: refactor driver for imx93 Date: Wed, 31 Jan 2024 13:58:07 +0800 Message-Id: <20240131055811.3035741-2-xu.yang_2@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131055811.3035741-1-xu.yang_2@nxp.com> References: <20240131055811.3035741-1-xu.yang_2@nxp.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SI2PR02CA0041.apcprd02.prod.outlook.com (2603:1096:4:196::20) To DU2PR04MB8822.eurprd04.prod.outlook.com (2603:10a6:10:2e1::11) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU2PR04MB8822:EE_|DU2PR04MB8917:EE_ X-MS-Office365-Filtering-Correlation-Id: 7ee530a6-e1c3-41ff-7f2c-08dc2220b94e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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However, some macro definitions and events are different on these two Socs. For preparing imx95 supports, this will refactor driver for imx93. Signed-off-by: Xu Yang --- Changes in v4: - new patch --- drivers/perf/fsl_imx9_ddr_perf.c | 121 ++++++++++++++++++++++--------- 1 file changed, 87 insertions(+), 34 deletions(-) diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c index 9685645bfe04..b1a58e9e1617 100644 --- a/drivers/perf/fsl_imx9_ddr_perf.c +++ b/drivers/perf/fsl_imx9_ddr_perf.c @@ -11,14 +11,14 @@ #include /* Performance monitor configuration */ -#define PMCFG1 0x00 -#define PMCFG1_RD_TRANS_FILT_EN BIT(31) -#define PMCFG1_WR_TRANS_FILT_EN BIT(30) -#define PMCFG1_RD_BT_FILT_EN BIT(29) -#define PMCFG1_ID_MASK GENMASK(17, 0) +#define PMCFG1 0x00 +#define MX93_PMCFG1_RD_TRANS_FILT_EN BIT(31) +#define MX93_PMCFG1_WR_TRANS_FILT_EN BIT(30) +#define MX93_PMCFG1_RD_BT_FILT_EN BIT(29) +#define MX93_PMCFG1_ID_MASK GENMASK(17, 0) -#define PMCFG2 0x04 -#define PMCFG2_ID GENMASK(17, 0) +#define PMCFG2 0x04 +#define MX93_PMCFG2_ID GENMASK(17, 0) /* Global control register affects all counters and takes priority over local control registers */ #define PMGC0 0x40 @@ -51,6 +51,7 @@ static DEFINE_IDA(ddr_ida); struct imx_ddr_devtype_data { const char *identifier; /* system PMU identifier for userspace */ + struct attribute **attrs; /* AXI filter attributes */ }; struct ddr_pmu { @@ -67,16 +68,6 @@ struct ddr_pmu { int id; }; -static const struct imx_ddr_devtype_data imx93_devtype_data = { - .identifier = "imx93", -}; - -static const struct of_device_id imx_ddr_pmu_dt_ids[] = { - {.compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data}, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids); - static ssize_t ddr_perf_identifier_show(struct device *dev, struct device_attribute *attr, char *page) @@ -178,7 +169,6 @@ static struct attribute *ddr_perf_events_attrs[] = { IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_6, 70), IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_7, 71), IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_empty, 72), - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, 73), /* counter3 specific events */ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_0, 64), @@ -190,7 +180,6 @@ static struct attribute *ddr_perf_events_attrs[] = { IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_6, 70), IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_7, 71), IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_full, 72), - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, 73), /* counter4 specific events */ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_0, 64), @@ -202,7 +191,6 @@ static struct attribute *ddr_perf_events_attrs[] = { IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_6, 70), IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_7, 71), IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2_rmw, 72), - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, 73), /* counter5 specific events */ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_0, 64), @@ -242,6 +230,16 @@ static const struct attribute_group ddr_perf_events_attr_group = { .attrs = ddr_perf_events_attrs, }; +static struct attribute *imx93_ddr_perf_events_attrs[] = { + /* counter2 specific events */ + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, 73), + /* counter3 specific events */ + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, 73), + /* counter4 specific events */ + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, 73), + NULL, +}; + PMU_FORMAT_ATTR(event, "config:0-7"); PMU_FORMAT_ATTR(counter, "config:8-15"); PMU_FORMAT_ATTR(axi_id, "config1:0-17"); @@ -268,6 +266,22 @@ static const struct attribute_group *attr_groups[] = { NULL, }; +static const struct imx_ddr_devtype_data imx93_devtype_data = { + .identifier = "imx93", + .attrs = imx93_ddr_perf_events_attrs, +}; + +static const struct of_device_id imx_ddr_pmu_dt_ids[] = { + { .compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids); + +static inline bool is_imx93(struct ddr_pmu *pmu) +{ + return pmu->devtype_data == &imx93_devtype_data; +} + static void ddr_perf_clear_counter(struct ddr_pmu *pmu, int counter) { if (counter == CYCLES_COUNTER) { @@ -361,7 +375,7 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config, } } -static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int cfg2) +static void imx93_ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int cfg2) { u32 pmcfg1, pmcfg2; int event, counter; @@ -372,27 +386,27 @@ static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int pmcfg1 = readl_relaxed(pmu->base + PMCFG1); if (counter == 2 && event == 73) - pmcfg1 |= PMCFG1_RD_TRANS_FILT_EN; + pmcfg1 |= MX93_PMCFG1_RD_TRANS_FILT_EN; else if (counter == 2 && event != 73) - pmcfg1 &= ~PMCFG1_RD_TRANS_FILT_EN; + pmcfg1 &= ~MX93_PMCFG1_RD_TRANS_FILT_EN; if (counter == 3 && event == 73) - pmcfg1 |= PMCFG1_WR_TRANS_FILT_EN; + pmcfg1 |= MX93_PMCFG1_WR_TRANS_FILT_EN; else if (counter == 3 && event != 73) - pmcfg1 &= ~PMCFG1_WR_TRANS_FILT_EN; + pmcfg1 &= ~MX93_PMCFG1_WR_TRANS_FILT_EN; if (counter == 4 && event == 73) - pmcfg1 |= PMCFG1_RD_BT_FILT_EN; + pmcfg1 |= MX93_PMCFG1_RD_BT_FILT_EN; else if (counter == 4 && event != 73) - pmcfg1 &= ~PMCFG1_RD_BT_FILT_EN; + pmcfg1 &= ~MX93_PMCFG1_RD_BT_FILT_EN; - pmcfg1 &= ~FIELD_PREP(PMCFG1_ID_MASK, 0x3FFFF); - pmcfg1 |= FIELD_PREP(PMCFG1_ID_MASK, cfg2); + pmcfg1 &= ~FIELD_PREP(MX93_PMCFG1_ID_MASK, 0x3FFFF); + pmcfg1 |= FIELD_PREP(MX93_PMCFG1_ID_MASK, cfg2); writel(pmcfg1, pmu->base + PMCFG1); pmcfg2 = readl_relaxed(pmu->base + PMCFG2); - pmcfg2 &= ~FIELD_PREP(PMCFG2_ID, 0x3FFFF); - pmcfg2 |= FIELD_PREP(PMCFG2_ID, cfg1); + pmcfg2 &= ~FIELD_PREP(MX93_PMCFG2_ID, 0x3FFFF); + pmcfg2 |= FIELD_PREP(MX93_PMCFG2_ID, cfg1); writel(pmcfg2, pmu->base + PMCFG2); } @@ -476,12 +490,12 @@ static int ddr_perf_event_add(struct perf_event *event, int flags) hwc->idx = counter; hwc->state |= PERF_HES_STOPPED; + /* read trans, write trans, read beat */ + imx93_ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2); + if (flags & PERF_EF_START) ddr_perf_event_start(event, flags); - /* read trans, write trans, read beat */ - ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2); - return 0; } @@ -596,6 +610,39 @@ static int ddr_perf_offline_cpu(unsigned int cpu, struct hlist_node *node) return 0; } +static int ddr_perf_add_events(struct ddr_pmu *pmu) +{ + int i, ret; + struct attribute **attrs = pmu->devtype_data->attrs; + struct device *pmu_dev = pmu->pmu.dev; + + if (!attrs) + return 0; + + for (i = 0; attrs[i]; i++) { + ret = sysfs_add_file_to_group(&pmu_dev->kobj, attrs[i], "events"); + if (ret) { + dev_warn(pmu->dev, "i.MX9 DDR Perf add events failed (%d)\n", ret); + return ret; + } + } + + return 0; +} + +static void ddr_perf_remove_events(struct ddr_pmu *pmu) +{ + int i; + struct attribute **attrs = pmu->devtype_data->attrs; + struct device *pmu_dev = pmu->pmu.dev; + + if (!attrs) + return; + + for (i = 0; attrs[i]; i++) + sysfs_remove_file_from_group(&pmu_dev->kobj, attrs[i], "events"); +} + static int ddr_perf_probe(struct platform_device *pdev) { struct ddr_pmu *pmu; @@ -666,6 +713,10 @@ static int ddr_perf_probe(struct platform_device *pdev) if (ret) goto ddr_perf_err; + ret = ddr_perf_add_events(pmu); + if (ret) + dev_warn(&pdev->dev, "i.MX9 DDR Perf filter events are missing\n"); + return 0; ddr_perf_err: @@ -683,6 +734,8 @@ static int ddr_perf_remove(struct platform_device *pdev) { struct ddr_pmu *pmu = platform_get_drvdata(pdev); + ddr_perf_remove_events(pmu); + cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node); cpuhp_remove_multi_state(pmu->cpuhp_state); -- 2.34.1