Received-SPF: pass (google.com: domain of linux-kernel+bounces-45788-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) client-ip=147.75.80.249;
From: Xu Yang <xu.yang_2@nxp.com>
To: Frank.li@nxp.com,
	will@kernel.org,
	mark.rutland@arm.com,
	robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org,
	conor+dt@kernel.org,
	shawnguo@kernel.org,
	s.hauer@pengutronix.de,
	kernel@pengutronix.de,
	festevam@gmail.com,
	john.g.garry@oracle.com,
	jolsa@kernel.org,
	namhyung@kernel.org,
	irogers@google.com
Cc: linux-imx@nxp.com,
	mike.leach@linaro.org,
	leo.yan@linaro.org,
	peterz@infradead.org,
	mingo@redhat.com,
	acme@kernel.org,
	alexander.shishkin@linux.intel.com,
	adrian.hunter@intel.com,
	xu.yang_2@nxp.com,
	linux-arm-kernel@lists.infradead.org,
	devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-perf-users@vger.kernel.org,
	imx@lists.linux.dev
Subject: [PATCH v4 5/6] perf: imx_perf: limit counter ID from user space and optimize counter usage
Date: Wed, 31 Jan 2024 13:58:10 +0800
Message-Id: <20240131055811.3035741-5-xu.yang_2@nxp.com>
In-Reply-To: <20240131055811.3035741-1-xu.yang_2@nxp.com>
References: <20240131055811.3035741-1-xu.yang_2@nxp.com>
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
Precedence: bulk
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0:
	=?us-ascii?Q?Ufg9od1pygUSCJAeNbBaQDJmM//ZUKpr06D3FQw52XHVShsbwFArt11ZVNiv?=
 =?us-ascii?Q?GV8EIDrMUzcGFvaKJaKlzd57S5anuvJ+XKaFqMYZ/h8ZlhS9gFd4eP48jK6e?=
 =?us-ascii?Q?1TogpCg4oQAO1rFNRK0mwqUaEg86d9dEpVDjUGDwZhw9VW8VMyKJoztwcF59?=
 =?us-ascii?Q?PeIt2Y5QqZrUNL6pO3f70Ti4FglrWzdXZrxKEviAacUNtjkrWruOudGt9Xmd?=
 =?us-ascii?Q?Q9M8HllbUk45MwTrfSd4kVHssYZnj6IvqIt9j3fvaAU7BctEhUFuY/MLTmDn?=
 =?us-ascii?Q?ZGMjMmpSeayOJ7wSBuTE5B5OC647A7hXCpl11FC6YJasD7muYW32elrqH7wf?=
 =?us-ascii?Q?xLGjqCFivzwbLyCNrNpUKZGaF2tWvkgmZoUhCL01jzSzhMhvDDS9vWmhxDTB?=
 =?us-ascii?Q?FGxCPpM6jOcCmE1lOh+dR6WXZoBz+GpnVFIy6S79/5HgnR3EJUa7aQdEv1ff?=
 =?us-ascii?Q?gNE+qfhO93DZpDB89ymUBzhDFgRGCF0ouphS/LAYczCsvgsYKmWPNMdCB5JP?=
 =?us-ascii?Q?bfdD+tRYFwRIFXxDSXCzG3SFwZqoCgVZqmccOkrvWTbdRm9g4Ny6aSi9e//h?=
 =?us-ascii?Q?WnUpyKOZGoeYor6pEpx2WvXdPJvfH0c6qpuK0m8fia5HhBA0E0KA44qFhAZR?=
 =?us-ascii?Q?zLvNq2YbNBwS4tnp/o0xTkoCxwDONd/oVG8bLXe2ifW6PP0zPmzlJ0Rqys4A?=
 =?us-ascii?Q?Yk87UYW5AC2h2tf8wgVX9eCEJwAj6Fqq5cz1Cnbdq7U32cYJH1f2sHovuuyo?=
 =?us-ascii?Q?an0C14oS573u40yBO6LULfaFz+ZZXLgzJXDdbVE6p4BTNMnu5y/BP3JctNfh?=
 =?us-ascii?Q?cNeXqIGVUeToZzByw7m7BnMuskSnsFuyhXUeWk3BKaIMjAp6cEMitThoB8CA?=
 =?us-ascii?Q?BxbUPtaHI527QfOnxKoU8lVsAqPujW9HfVBOQSV76oVHVGmwyiiywzwcXRHt?=
 =?us-ascii?Q?A62Yw3nam3PBjw/bXhrIzBDqBLzpc4M6ZJ6m9T8+7cQRvESO2vaRCWYnihUQ?=
 =?us-ascii?Q?BTqOnIQvFw5bgprtop9bzNklfDgVpM7XteSj/vugrsgzMZKg93GYZv53oN51?=
 =?us-ascii?Q?df347l9yvqPkUhMb8yglyU1F4R+NAYRhFkdOV9+MH96pw2VvZruPtraktUmD?=
 =?us-ascii?Q?nj/1XeVjkSw/zu3P3ZspoKiLn1t6p2TX7iio9FhKRvgf4K5YQ6gNLvhVgQ42?=
 =?us-ascii?Q?GtoolWRTCqN13zTWNjppeBjbIYKhZfQpp/Gad/BEO8nRcklRreXNKVX/byY0?=
 =?us-ascii?Q?YJl14tDfzLwveZ8NsPCHAaFmR+yQlo6G7QN11io2Nk7TSpfnYmtgf1TSEudB?=
 =?us-ascii?Q?+mNtnkrxnjKu3e/7fLVi8/xpUhWK8KtLpnkW7+2pHQmOVVJPFD31UgyGowDw?=
 =?us-ascii?Q?5a5VmzqGvZJbux5rVS6gu49KsfoEyvaoZJcjcM73HY/HoDcmTg4D5HxWTwtP?=
 =?us-ascii?Q?yuzhM1fH4PCgKdLOyPGpojdDGvE/4HULk+EWnDB6vEvpTz8XixQNDPGjZe5l?=
 =?us-ascii?Q?zM9yliFBhQ8FNxWTomhPRsFv7BPWGaQs1XOt3g8ZSs3TLjAwskNsQg8jZa4l?=
 =?us-ascii?Q?Hv0IxDcgI7xd2keBjy5wXsYWy7OHVeN9gvWt4xYt?=
X-OriginatorOrg: nxp.com
X-MS-Exchange-CrossTenant-Network-Message-Id: b34f514c-3b21-4c2e-7fba-08dc2220c732
X-MS-Exchange-CrossTenant-AuthSource: DU2PR04MB8822.eurprd04.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Jan 2024 05:52:15.7731
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: tg2VMKrPwC7vjfs25GieTCub/iNKYUpz8kd8ncHyf6fHG+reCeoJE/J5SXxj2BLDA/HFB/9zh4xxjUvY0Z64eg==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR04MB8917

The user can pass any counter ID to perf app. However, current pmu driver
doesn't judge the validity of the counter ID. This will add necessary
check for counter ID from user space. Besides, this pmu has 10 counters
except cycle counter which can be used to count reference events and
counter specific evnets. This will also add supports to auto allocate
counter if the user doesn't pass it the perf. Then, the usage of counter
will be optimized.

Signed-off-by: Xu Yang <xu.yang_2@nxp.com>

---
Changes in v2:
 - limit counter ID from user to 0-10
 - combine dynamic and static allocation of counter
Changes in v3:
 - no changes
Changes in v4:
 - rename ddr_perf_is_specific_event()
 - use macro definitions to parse config attr
---
 drivers/perf/fsl_imx9_ddr_perf.c | 72 +++++++++++++++++++++++++++++++-
 1 file changed, 71 insertions(+), 1 deletion(-)

diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c
index 94041f06c152..e71496809c52 100644
--- a/drivers/perf/fsl_imx9_ddr_perf.c
+++ b/drivers/perf/fsl_imx9_ddr_perf.c
@@ -51,6 +51,7 @@
 
 #define NUM_COUNTERS		11
 #define CYCLES_COUNTER		0
+#define CYCLES_EVENT_ID		0
 
 #define CONFIG_EVENT_MASK	0x00FF
 #define CONFIG_EVENT_OFFSET	0
@@ -240,6 +241,19 @@ static struct attribute *ddr_perf_events_attrs[] = {
 	NULL,
 };
 
+/*
+ * An event is either reference evnet or counter specific event.
+ * For counter specific event, the event count will only be incremented
+ * on the corresponding counter.
+ */
+static bool ddr_perf_is_counter_specific_event(int event)
+{
+	if (event >= 64 && event <= 73)
+		return true;
+	else
+		return false;
+}
+
 static const struct attribute_group ddr_perf_events_attr_group = {
 	.name = "events",
 	.attrs = ddr_perf_events_attrs,
@@ -514,6 +528,7 @@ static int ddr_perf_event_init(struct perf_event *event)
 	struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
 	struct hw_perf_event *hwc = &event->hw;
 	struct perf_event *sibling;
+	int event_id, counter;
 
 	if (event->attr.type != event->pmu->type)
 		return -ENOENT;
@@ -526,6 +541,18 @@ static int ddr_perf_event_init(struct perf_event *event)
 		return -EOPNOTSUPP;
 	}
 
+	counter = (event->attr.config & CONFIG_COUNTER_MASK) >> CONFIG_COUNTER_OFFSET;
+	if (counter > NUM_COUNTERS) {
+		dev_warn(pmu->dev, "Only counter 0-10 is supported!\n");
+		return -EINVAL;
+	}
+
+	event_id = (event->attr.config & CONFIG_EVENT_MASK) >> CONFIG_EVENT_OFFSET;
+	if (ddr_perf_is_counter_specific_event(event_id) && counter == 0) {
+		dev_err(pmu->dev, "Need specify counter for counter specific events!\n");
+		return -EINVAL;
+	}
+
 	/*
 	 * We must NOT create groups containing mixed PMUs, although software
 	 * events are acceptable (for example to create a CCN group
@@ -559,6 +586,39 @@ static void ddr_perf_event_start(struct perf_event *event, int flags)
 	hwc->state = 0;
 }
 
+static int ddr_perf_alloc_counter(struct ddr_pmu *pmu, int event, int counter)
+{
+	int i;
+
+	if (event == CYCLES_EVENT_ID) {
+		/*
+		 * Always map cycle event to counter 0.
+		 * Cycles counter is dedicated for cycle event
+		 * can't used for the other counters.
+		 */
+		if (pmu->events[CYCLES_COUNTER] == NULL)
+			return CYCLES_COUNTER;
+	} else if (counter != 0) {
+		/*
+		 * 1. ddr_perf_event_init() will make sure counter
+		 *    is not 0 for counter specific events.
+		 * 2. Allow specify counter for referene event too.
+		 */
+		if (pmu->events[counter] == NULL)
+			return counter;
+	} else {
+		/*
+		 * Counter may be 0 if user doesn't specify it.
+		 * Auto allocate counter for referene event.
+		 */
+		for (i = 1; i < NUM_COUNTERS; i++)
+			if (pmu->events[i] == NULL)
+				return i;
+	}
+
+	return -ENOENT;
+}
+
 static int ddr_perf_event_add(struct perf_event *event, int flags)
 {
 	struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
@@ -566,10 +626,18 @@ static int ddr_perf_event_add(struct perf_event *event, int flags)
 	int cfg = event->attr.config;
 	int cfg1 = event->attr.config1;
 	int cfg2 = event->attr.config2;
-	int counter;
+	int event_id, counter;
 
+	event_id = (cfg & CONFIG_EVENT_MASK) >> CONFIG_EVENT_OFFSET;
 	counter = (cfg & CONFIG_COUNTER_MASK) >> CONFIG_COUNTER_OFFSET;
 
+	/* check if counter is available or needs to allocate one */
+	counter = ddr_perf_alloc_counter(pmu, event_id, counter);
+	if (counter < 0) {
+		dev_dbg(pmu->dev, "There are not enough counters\n");
+		return -EOPNOTSUPP;
+	}
+
 	pmu->events[counter] = event;
 	pmu->active_events++;
 	hwc->idx = counter;
@@ -604,9 +672,11 @@ static void ddr_perf_event_del(struct perf_event *event, int flags)
 {
 	struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
 	struct hw_perf_event *hwc = &event->hw;
+	int counter = hwc->idx;
 
 	ddr_perf_event_stop(event, PERF_EF_UPDATE);
 
+	pmu->events[counter] = NULL;
 	pmu->active_events--;
 	hwc->idx = -1;
 }
-- 
2.34.1