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b=XsLxGdHLHopqrkaVajMFEdmHeE3cazOp2IuB1487+JuANOoOeRp4hxibAKpJT5jz5eWeces2x0sekRzxYHi2H9i91bTUK0mBa4Z40Gn5Cyp7TmTRJoTxQzWYSBtw5AuMObThUHNNAAhGkJ9LhdsmO6d+wamAXo9S7mPltTtvqoM= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from DU2PR04MB8822.eurprd04.prod.outlook.com (2603:10a6:10:2e1::11) by DU2PR04MB8917.eurprd04.prod.outlook.com (2603:10a6:10:2e0::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7249.24; Wed, 31 Jan 2024 05:52:08 +0000 Received: from DU2PR04MB8822.eurprd04.prod.outlook.com ([fe80::d45f:4483:c11:68b0]) by DU2PR04MB8822.eurprd04.prod.outlook.com ([fe80::d45f:4483:c11:68b0%7]) with mapi id 15.20.7228.029; Wed, 31 Jan 2024 05:52:08 +0000 From: Xu Yang To: Frank.li@nxp.com, will@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, john.g.garry@oracle.com, jolsa@kernel.org, namhyung@kernel.org, irogers@google.com Cc: linux-imx@nxp.com, mike.leach@linaro.org, leo.yan@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, alexander.shishkin@linux.intel.com, adrian.hunter@intel.com, xu.yang_2@nxp.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, imx@lists.linux.dev Subject: [PATCH v4 4/6] perf: imx_perf: add macro definitions for parsing config attr Date: Wed, 31 Jan 2024 13:58:09 +0800 Message-Id: <20240131055811.3035741-4-xu.yang_2@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131055811.3035741-1-xu.yang_2@nxp.com> References: <20240131055811.3035741-1-xu.yang_2@nxp.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SI2PR02CA0041.apcprd02.prod.outlook.com (2603:1096:4:196::20) To DU2PR04MB8822.eurprd04.prod.outlook.com (2603:10a6:10:2e1::11) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU2PR04MB8822:EE_|DU2PR04MB8917:EE_ X-MS-Office365-Filtering-Correlation-Id: 3dad1156-7f86-427d-23c7-08dc2220c290 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?Gm4ECq5KKgCSNHlXc9e21zuKAnBiamcuTTzHU46pDSWRtEdsRJMKltuKrxVz?= =?us-ascii?Q?hdzchwvsSHIbilj4nvOUq/HTz2lsEWzvdnbJdLO/iZ6M7nJAhR49ZDdgYotI?= =?us-ascii?Q?NjUlqXjHnqKZ/WyVvkd7XMXoU3A6p3XdoXQzwOPr7ZoMBKINTJoazXQjqifB?= =?us-ascii?Q?p2G51cdzX88jXe5tyHZzbpGCCyGYDCe2SIMQ5aZhlAnN/HfpRG4FqaXSAme9?= =?us-ascii?Q?zVKEQ3LTYNAiHb+zfeIBiSiB5wwKu2unXmyT0nm1MT1p1Ilz1BRP1VRkg8xS?= =?us-ascii?Q?Gc9Kq/PKFuEbbUj5ZnithhXshYWSzcaXxf2VMI5zPsbMgzAALlQhz47of0jD?= =?us-ascii?Q?MTm0Xuzq+vNtci8ZF8bk/V7t7ZwCwSdp5waQPdtU2NG+T4eMNOkTexc9gYNh?= =?us-ascii?Q?q84vUummCe0m/FpF5KjRqYFYyKPsbIYlfYvBroqq/lsTuapeP1OTZ7P5P+a0?= =?us-ascii?Q?D6m1IAKIBnuv/YixVUEQE3/P+WhOQI4MpNTSKZ1Q8ZJBqLobPEYmmNkUfPPQ?= =?us-ascii?Q?ERNPp5D2O0rM30nytYMWRXu8lEVwbby3ufWXnd9dw9P+rjjG+3/ci3qmQXcK?= =?us-ascii?Q?em2tGjwXqUEg0XfUJfVx92HoDstJm/CWQRzWEaom3tCZgrkv/SWbgR6mnnjF?= =?us-ascii?Q?XCPCGpA0yALLR49zhJs8ovizdwcaYpaXGqJUG3RjO5l6//MYGtXnOW4WpnPQ?= =?us-ascii?Q?aZuotOpunY7ZQoip4PEB8HiAQjNy+dtrb8mR+xploDctj8b/AVUCJORTCy41?= =?us-ascii?Q?OJtU2awmDb3W+2dsDyX4788w6GwUkaxCue7a61AqmtaH58Os8lnw7/OllBKq?= =?us-ascii?Q?PiFgY9tdhSHH9ZMaU58YeoLijOop1d+TJ1OtjdYQWi0+tNru7T90Qtf5jAI8?= =?us-ascii?Q?FHQWSFn35EQZhbqPUzlwuDrMV1Dhcdx6t+Y9XoxZ42fhGORLgVh/UGqvG75d?= =?us-ascii?Q?nkjKqLYl81OZfMEGFdD76dxbW8tGTpqGb8dmQ5PgWSYeC6Ef5JF6fL+h37lW?= =?us-ascii?Q?7bhuxVOE6DSx7mLTL99W8Jak8Ddk/HaOGvg/wnumLNzB+pxzPuJuTjseN8t/?= =?us-ascii?Q?ESW6djjbnVPHW6fnHEU7iATufRgF5vu8mGLMGuZDdKcBtlzfAZOjiP2yOVrr?= =?us-ascii?Q?CucVjfC3VAdiuKn3IG7UrzWvcBJRz5N6nz3K/Dw/Qtp2VPEtrws0lO+67FVW?= =?us-ascii?Q?SYqD5WC702gTE/XMBirUFEeIF3az8ZQKBq2hHpSbaHwLMW7x559sxC15JYiC?= =?us-ascii?Q?PJUy71uhi9bkForMhE5DNrFrykL1NPK5zusAJzNJSYCtbzga2wDubGLVjLro?= =?us-ascii?Q?sb+yLGBt2SI/uwNevrNI4lyT0832F2gDYjO+c6y9JpSLahUY7NTBSxSZ1k5F?= =?us-ascii?Q?y/I7Y/lr9cfTdN/P7iS2XPtpX5EdM0mrnUClM4UMcNSTfIf7qSZ2W1RVdbvI?= =?us-ascii?Q?BVm5kNS98fWPyZe0axtTPLhWvt/I+FJPM8pIqguYWtCPCG/ypmawjXNpTlOa?= =?us-ascii?Q?jt+zDSiDXxmNKBx3AT2Gj2d1Ao7peFVGpMf+BBf3vlfFohwbSMmeY1I8auAH?= =?us-ascii?Q?/urxX3BgHqOYJh7Sh4t7V/0ex9EiLm058cZ45/Ff?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3dad1156-7f86-427d-23c7-08dc2220c290 X-MS-Exchange-CrossTenant-AuthSource: DU2PR04MB8822.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Jan 2024 05:52:08.1204 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: nCcWPYYfaEKNV2+U6AVmIzfcNGHGXqybIuy2DquXhwHrTpOMeg55OZin/MzvV7vxyiuXPIhjQCqjG4VesDRa9Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR04MB8917 The user can set event and counter in cmdline and the driver need to parse it using 'config' attr value. This will add macro definitions to avoid hard-code in driver. Signed-off-by: Xu Yang --- Changes in v4: - new patch --- drivers/perf/fsl_imx9_ddr_perf.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c index 85aaaef7212f..94041f06c152 100644 --- a/drivers/perf/fsl_imx9_ddr_perf.c +++ b/drivers/perf/fsl_imx9_ddr_perf.c @@ -52,6 +52,11 @@ #define NUM_COUNTERS 11 #define CYCLES_COUNTER 0 +#define CONFIG_EVENT_MASK 0x00FF +#define CONFIG_EVENT_OFFSET 0 +#define CONFIG_COUNTER_MASK 0xFF00 +#define CONFIG_COUNTER_OFFSET 8 + #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu) #define DDR_PERF_DEV_NAME "imx9_ddr" @@ -381,8 +386,10 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config, int counter, bool enable) { u32 ctrl_a; + int event; ctrl_a = readl_relaxed(pmu->base + PMLCA(counter)); + event = (config & CONFIG_EVENT_MASK) >> CONFIG_EVENT_OFFSET; if (enable) { ctrl_a |= PMLCA_FC; @@ -394,7 +401,7 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config, ctrl_a &= ~PMLCA_FC; ctrl_a |= PMLCA_CE; ctrl_a &= ~FIELD_PREP(PMLCA_EVENT, 0x7F); - ctrl_a |= FIELD_PREP(PMLCA_EVENT, (config & 0x000000FF)); + ctrl_a |= FIELD_PREP(PMLCA_EVENT, event); writel(ctrl_a, pmu->base + PMLCA(counter)); } else { /* Freeze counter. */ @@ -408,8 +415,8 @@ static void imx93_ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1 u32 pmcfg1, pmcfg2; int event, counter; - event = cfg & 0x000000FF; - counter = (cfg & 0x0000FF00) >> 8; + event = (cfg & CONFIG_EVENT_MASK) >> CONFIG_EVENT_OFFSET; + counter = (cfg & CONFIG_COUNTER_MASK) >> CONFIG_COUNTER_OFFSET; pmcfg1 = readl_relaxed(pmu->base + PMCFG1); @@ -443,8 +450,8 @@ static void imx95_ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1 u32 pmcfg1, pmcfg, offset = 0; int event, counter; - event = cfg & 0x000000FF; - counter = (cfg & 0x0000FF00) >> 8; + event = (cfg & CONFIG_EVENT_MASK) >> CONFIG_EVENT_OFFSET; + counter = (cfg & CONFIG_COUNTER_MASK) >> CONFIG_COUNTER_OFFSET; pmcfg1 = readl_relaxed(pmu->base + PMCFG1); @@ -561,7 +568,7 @@ static int ddr_perf_event_add(struct perf_event *event, int flags) int cfg2 = event->attr.config2; int counter; - counter = (cfg & 0x0000FF00) >> 8; + counter = (cfg & CONFIG_COUNTER_MASK) >> CONFIG_COUNTER_OFFSET; pmu->events[counter] = event; pmu->active_events++; -- 2.34.1