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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000FCC5.mail.protection.outlook.com (10.167.242.107) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7181.13 via Frontend Transport; Wed, 31 Jan 2024 08:50:36 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Wed, 31 Jan 2024 02:50:33 -0600 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH 0/6] AMD Pstate Fixes And Enhancements Date: Wed, 31 Jan 2024 16:50:15 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000FCC5:EE_|CY8PR12MB8244:EE_ X-MS-Office365-Filtering-Correlation-Id: 977e7313-c533-4e7e-5af9-08dc2239b1ab X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Jan 2024 08:50:36.8107 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 977e7313-c533-4e7e-5af9-08dc2239b1ab X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC5.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8244 The patch series adds some fixes and enhancements to the AMD pstate driver. It enables CPPC v2 for certain processors in the family 17H, as requested by TR40 processor users who expect improved performance and lower system temperature. Additionally, it fixes the initialization of nominal_freq for each cpudata and changes latency and delay values to be read from platform firmware firstly for more accurate timing. A new quirk is also added for legacy processors that lack CPPC capabilities, which caused the pstate driver to fail loading. I would greatly appreciate any feedbacks. Thank you! Perry Yuan (6): ACPI: CPPC: enable AMD CPPC V2 support for family 17h processors cpufreq:amd-pstate: fix the nominal freq value set cpufreq:amd-pstate: initialize nominal_freq of each cpudata cpufreq:amd-pstate: get pstate transition delay and latency value from ACPI tables cppc_acpi: print error message if CPPC is unsupported cpufreq:amd-pstate: add quirk for the pstate CPPC capabilities missing arch/x86/kernel/acpi/cppc.c | 2 +- drivers/acpi/cppc_acpi.c | 6 +- drivers/cpufreq/amd-pstate.c | 112 ++++++++++++++++++++++++++++------- include/linux/amd-pstate.h | 6 ++ 4 files changed, 102 insertions(+), 24 deletions(-) -- 2.34.1