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Wed, 31 Jan 2024 02:00:07 -0800 (PST) Received: from localhost ([122.172.83.95]) by smtp.gmail.com with ESMTPSA id dj15-20020a17090ad2cf00b00295e041baf5sm1051645pjb.2.2024.01.31.02.00.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jan 2024 02:00:07 -0800 (PST) Date: Wed, 31 Jan 2024 15:30:04 +0530 From: Viresh Kumar To: Manivannan Sadhasivam Cc: Krishna chaitanya chundru , Bjorn Andersson , Konrad Dybcio , Bjorn Helgaas , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rob Herring , Johan Hovold , Brian Masney , Georgi Djakov , linux-arm-msm@vger.kernel.org, vireshk@kernel.org, quic_vbadigan@quicinc.com, quic_skananth@quicinc.com, quic_nitegupt@quicinc.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v6 5/6] arm64: dts: qcom: sm8450: Add opp table support to PCIe Message-ID: <20240131100004.uqx6vaucojqo4kyg@vireshk-i7> References: <20240112-opp_support-v6-5-77bbf7d0cc37@quicinc.com> <20240129160420.GA27739@thinkpad> <20240130061111.eeo2fzaltpbh35sj@vireshk-i7> <20240130071449.GG32821@thinkpad> <20240130083619.lqbj47fl7aa5j3k5@vireshk-i7> <20240130094804.GD83288@thinkpad> <20240130095508.zgufudflizrpxqhy@vireshk-i7> <20240130131625.GA2554@thinkpad> <20240131052335.6nqpmccgr64voque@vireshk-i7> <20240131084645.GA3481@thinkpad> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240131084645.GA3481@thinkpad> On 31-01-24, 14:16, Manivannan Sadhasivam wrote: > Most of the hits are from CPU nodes... For some reasons, peripheral drivers are > sticking to hardcoded values. I guess the reason for this is that the OPP core wasn't used for non-CPU devices until recently. And we are in a transition phase where few of the drivers will migrate to using it and so will have DT based bw values. -- viresh