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charset="utf-8" X-Developer-Signature: v=1; a=openpgp-sha256; l=1081; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=QpjxKADVuxDHO2HHz1mJLhLzOw0DBvtxFU1iut/HhaM=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDKm7bCyjD5d2OlRF8PLW7+z+duVV4xQZhtszgq8axl4Ib TJrlfnYUcrCIMbBICumyJJ4u69Fav0flx3OPW9h5rAygQxh4OIUgIlcmsrIsHbKbM4q7dOH3UPN g3u+C264YKjs8PpRb9Lv5o67C2V3dTEy7Lv3YLK2exd3R1fLkZe5Lw8fvqb1xjF07uOUS1PsNP6 b8gIA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: 8bit From: Conor Dooley On Wed, 20 Dec 2023 23:17:38 +0200, Cristian Ciocaltea wrote: > This patch series adds ethernet support for the StarFive JH7100 SoC and > makes it available for the StarFive VisionFive V1 and BeagleV Starlight > boards, although I could only validate on the former SBC. Thank you Emil > and Geert for helping with tests on BeagleV! > > The work is heavily based on the reference implementation [1] and depends > on the SiFive Composable Cache controller and non-coherent DMA support > provided by Emil via [2] and [3]. > > [...] Applied to riscv-dt-for-next, thanks! [1/4] riscv: dts: starfive: jh7100: Add sysmain and gmac DT nodes https://git.kernel.org/conor/c/5ca37ca2a483 [2/4] riscv: dts: starfive: jh7100-common: Setup pinmux and enable gmac https://git.kernel.org/conor/c/6e204aa2116c [3/4] riscv: dts: starfive: visionfive-v1: Setup ethernet phy https://git.kernel.org/conor/c/e16d3dc0a2d7 [4/4] riscv: dts: starfive: beaglev-starlight: Setup phy reset gpio https://git.kernel.org/conor/c/2db68ddbf33a Thanks, Conor.