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Date: Thu, 01 Feb 2024 11:32:42 +0100
Message-Id: <CYTO9ZZ41LYD.170JY5PLQE7JE@bootlin.com>
Subject: Re: [PATCH v4 16/18] MIPS: mobileye: eyeq5: add reset properties to
 UARTs
Cc: "Vladimir Kondratiev" <vladimir.kondratiev@mobileye.com>,
 <linux-mips@vger.kernel.org>, <linux-clk@vger.kernel.org>,
 <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, "Thomas
 Petazzoni" <thomas.petazzoni@bootlin.com>, "Tawfik Bayouk"
 <tawfik.bayouk@mobileye.com>, <linux-gpio@vger.kernel.org>
To: "Krzysztof Kozlowski" <krzysztof.kozlowski@linaro.org>, "Gregory
 CLEMENT" <gregory.clement@bootlin.com>, "Michael Turquette"
 <mturquette@baylibre.com>, "Stephen Boyd" <sboyd@kernel.org>, "Rob Herring"
 <robh+dt@kernel.org>, "Krzysztof Kozlowski"
 <krzysztof.kozlowski+dt@linaro.org>, "Conor Dooley" <conor+dt@kernel.org>,
 "Thomas Bogendoerfer" <tsbogend@alpha.franken.de>, "Linus Walleij"
 <linus.walleij@linaro.org>, =?utf-8?q?Rafa=C5=82_Mi=C5=82ecki?=
 <rafal@milecki.pl>, "Philipp Zabel" <p.zabel@pengutronix.de>
From: =?utf-8?q?Th=C3=A9o_Lebrun?= <theo.lebrun@bootlin.com>
References: <20240131-mbly-clk-v4-0-bcd00510d6a0@bootlin.com>
 <20240131-mbly-clk-v4-16-bcd00510d6a0@bootlin.com>
 <3f3b1665-30d4-4581-84a8-7894a4a03b93@linaro.org>
In-Reply-To: <3f3b1665-30d4-4581-84a8-7894a4a03b93@linaro.org>

Hello,

On Thu Feb 1, 2024 at 10:13 AM CET, Krzysztof Kozlowski wrote:
> On 31/01/2024 17:26, Th=C3=A9o Lebrun wrote:
> > UART nodes have been added to the devicetree by the initial platform
> > support patch series. Add reset properties now that the reset node is
> > declared.
> >=20
> > Signed-off-by: Th=C3=A9o Lebrun <theo.lebrun@bootlin.com>
> > ---
> >  arch/mips/boot/dts/mobileye/eyeq5.dtsi | 3 +++
> >  1 file changed, 3 insertions(+)
> >=20
> > diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dt=
s/mobileye/eyeq5.dtsi
> > index 06e941b0ce10..ece71cafb6ee 100644
> > --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi
> > +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
> > @@ -78,6 +78,7 @@ uart0: serial@800000 {
> >  			interrupts =3D <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
> >  			clocks  =3D <&uart_clk>, <&occ_periph>;
> >  			clock-names =3D "uartclk", "apb_pclk";
> > +			resets =3D <&reset 0 10>;
>
> You touch the same file. Squash the patch with previous one. It's the
> same logical change to add reset to entire SoC. You don't add half of
> reset, right?

Makes sense. I'll update the commit message with that change.

Thanks,

--
Th=C3=A9o Lebrun, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com