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charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:y1z6Q7jXj+pqO1HZuYlxzuYbo5XGWT2nhBglJsaS3D/jXYPHO/E fqQckoUFrqWOYtFnR0avV/83ZiKtvFzTv0jNqDkQ4JQkSYb1R4TamPDpKXNjN/ArOiiFzUw zz54ZZENgvZguVYhLrfnI8TdVnyLp9SGIgiAOMryKrfSKWWH0/gDELEWzHvIOTEo1pVI+ZW WyQJhWE01UcOjxOi5rADA== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:pWne6h6kXCc=;pZaGvfKj0LTWoHMsy0FDDU4zrVI CewLpa8CIG3a3PXERoJlwqw5wE5gAL0HhZsj4pEcxrPQvzVCVfQSNrL5EPhEoFZmJRbcplvbO Cr4RQGG+PggquRYr3QnqvRhEEVsNfJ8blN83TiVomrrbUE3tDo4rfMOVLX+J9/QPtGxjP8KRG X6sTL5tZgtMjmONbS3Tfusw12GL9d9uwaIj7kiWolOyx8dOozA4MGW10/cc0NECcImpwo1yrI TgksSBZihpqet5jMBEa9imsZUFvGFEh3md2Bitg5AOQw0pr8AQ6dMlxasEC+ADew9ZTSSZmck IwZGJCEkg5gK6DcwhV8JS/fnCNn5Pa6YF5Qa6Tnpa/VMzZVvVUY/PaxM/mOuL79OacrFDYkI3 co5g4gco8F/LJ4AuBIwUTlXWrWTL0Nsv0IHVXnOlvvQUP124TL6mMPoENzEu5oS+kKiW1kdZc 4Dt4u/J3rW4/3ZGBLUeUF07OwXya0By3rfTCafR6UDBECjR7bLTD86S55bn9DrqmTblL/GjQY a68XW1M7h0d6ifO/98UR2YXp2eqP6G9RJu3nV155M86fPK4vA/DZfn5EopIz653pDnT/QYm/m nWFeupFQLb9JJuaH/GIhFjVJvpJhop7gU1Tc2vIt6S5iiAB6LZ6sSbJXw5ye/z8CeC/8XHC4s yrDK6lXHTNF1F27cFzLy+g9fvkKb9dDCRHaWSL9SsO68hLAFJQCy2zQ3uAZP9GT9UuyI74oPU X97C3XhX/ZKHMTvnfzMGtaQbu59TuCB5C/Rm2QQxZyXBZMuq+QrjQetUoOxTgU2GFJx3wSGbN 8bo840wwR7QOQi3H0YvPAUJzHxtS6gyeYT+fooHIZAwYw= Am 19=2E Januar 2024 18:04:36 MEZ schrieb Conor Dooley = : >On Fri, Jan 19, 2024 at 10:28:30AM +0100, AngeloGioacchino Del Regno wrot= e: >> >> The resets are organized on a per-reset-controller basis, so, the ETHWA= RP >> reset controller's first reset is RST_SWITCH, the second one is RST_som= ething_else, >> etc=2E while the first reset of the INFRA reset controller is PEXTP_MAC= _SWRST=2E >>=20 >> That's why ETHWARP has a reset index 0 and INFRA also starts at 0=2E >> I think that the numbering is good as it is, and having one driver star= t at index 5 >> while the other starts at index 12 would only overcomplicate registerin= g the resets >> in each driver, or waste bytes by making unnecessarily large arrays, fo= r (imo) no >> good reason=2E >>=20 >> This is one header, but it should "in theory" be more than one=2E=2E=2E= so we would have >> one for each hardware block - but that'd make the reset directory over-= crowded, as >> other MediaTek SoCs have got even more resets in even more hardware blo= cks than the >> MT7988=2E That'd be something like ~4 reset headers per SoC (and will i= ncrease with >> newer ones)=2E=2E=2E >> =2E=2E=2Eand this is why we have one binding header for resets=2E > >That's okay=2E The commit message leaves me, who clearly isn't a mediatek >guy, with no information as to why these are not one contiguous set=2E >IMO being for different reset controllers entirely is fine=2E > >> On the topic of leaving space to allow grouping RST0/RST1: -> No=2E <- >> The indices have to start from zero and have to be sequential, with no = holes=2E > >Agreed=2E Hi, Just a friendly reminder=2E As far as i understood, Patches are fine so far and do not need any rework= ,right? But i have not seen them picked up yet in linux-next=2E regards Frank