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From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date: Thu, 1 Feb 2024 13:05:05 +0000
Message-ID: <CA+V-a8tQRr96q6SJfCgPa7Zte4UhRHE+83hXNzN8-=rRX5EH0Q@mail.gmail.com>
Subject: Re: [PATCH 2/5] irqchip/renesas-rzg2l: Add support for RZ/Five SoC
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Thomas Gleixner <tglx@linutronix.de>, Rob Herring <robh+dt@kernel.org>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, 
	Magnus Damm <magnus.damm@gmail.com>, linux-renesas-soc@vger.kernel.org, 
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, 
	linux-kernel@vger.kernel.org, Biju Das <biju.das.jz@bp.renesas.com>, 
	Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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Hi Geert,

On Thu, Feb 1, 2024 at 8:34=E2=80=AFAM Geert Uytterhoeven <geert@linux-m68k=
org> wrote:
>
> Hi Prabhakar,
>
> On Wed, Jan 31, 2024 at 7:36=E2=80=AFPM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Tue, Jan 30, 2024 at 11:38=E2=80=AFAM Geert Uytterhoeven
> > <geert@linux-m68k.org> wrote:
> > > On Mon, Jan 29, 2024 at 4:16=E2=80=AFPM Prabhakar <prabhakar.csengg@g=
mail.com> wrote:
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > The IX45 block has additional mask registers (NMSK/IMSK/TMSK) as co=
mpared
> > > > to the RZ/G2L (family) SoC.
> > > >
> > > > Introduce masking/unmasking support for IRQ and TINT interrupts in =
IRQC
> > > > controller driver. Two new registers, IMSK and TMSK, are defined to
> > > > handle masking on RZ/Five SoC. The implementation utilizes a new da=
ta
> > > > structure, `struct rzg2l_irqc_data`, to determine mask support for =
a
> > > > specific controller instance.
> > > >
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.c=
om>
> > >
> > > > --- a/drivers/irqchip/irq-renesas-rzg2l.c
> > > > +++ b/drivers/irqchip/irq-renesas-rzg2l.c
> > > > @@ -66,15 +68,25 @@ struct rzg2l_irqc_reg_cache {
> > > >         u32     titsr[2];
> > > >  };
> > > >
> > > > +/**
> > > > + * struct rzg2l_irqc_data - OF data structure
> > > > + * @mask_supported: Indicates if mask registers are available
> > > > + */
> > > > +struct rzg2l_irqc_data {
> > >
> > > This structure has the same name as the single static struct
> > > rzg2l_irqc_priv instance, which is confusing.
> > >
> > Agreed, I will rename it to rzg2l_irqc_of_data
> >
> > > > +       bool    mask_supported;
> > > > +};
> > > > +
> > > >  /**
> > > >   * struct rzg2l_irqc_priv - IRQ controller private data structure
> > > >   * @base:      Controller's base address
> > > > + * @data:      OF data pointer
> > > >   * @fwspec:    IRQ firmware specific data
> > > >   * @lock:      Lock to serialize access to hardware registers
> > > >   * @cache:     Registers cache for suspend/resume
> > > >   */
> > > >  static struct rzg2l_irqc_priv {
> > > >         void __iomem                    *base;
> > > > +       const struct rzg2l_irqc_data    *data;
> > >
> > > Replacing this by a bool would avoid a pointer dereference in each us=
er,
> > > and allows you to make rzg2l_irqc_data etc. __initconst.
> > >
> > Do you mean just add "bool mask_supported" here and get rid of struct
> > rzg2l_irqc_data ? Can you please elaborate here..
>
> Either add "bool mask_supported" here, or add a copy of the full
> struct rzg2l_irqc_data (see below).
>
OK, i'll keep a copy of struct rzg2l_irqc_data here...
> >
> > > >         struct irq_fwspec               fwspec[IRQC_NUM_IRQ];
> > > >         raw_spinlock_t                  lock;
> > > >         struct rzg2l_irqc_reg_cache     cache;
> > >
> > > > @@ -371,9 +475,23 @@ static int rzg2l_irqc_parse_interrupts(struct =
rzg2l_irqc_priv *priv,
> > > >         return 0;
> > > >  }
> > > >
> > > > +static const struct rzg2l_irqc_data rzfive_irqc_data =3D {
> > > > +       .mask_supported =3D true,
> > > > +};
> > > > +
> > > > +static const struct rzg2l_irqc_data rzg2l_irqc_default_data =3D {
> > > > +       .mask_supported =3D false,
> > > > +};
> > > > +
> > > > +static const struct of_device_id rzg2l_irqc_matches[] =3D {
> > > > +       { .compatible =3D "renesas,r9a07g043f-irqc", .data =3D &rzf=
ive_irqc_data },
> > > > +       { }
> > > > +};
> > > > +
> > > >  static int rzg2l_irqc_init(struct device_node *node, struct device=
_node *parent)
> > > >  {
> > > >         struct irq_domain *irq_domain, *parent_domain;
> > > > +       const struct of_device_id *match;
> > > >         struct platform_device *pdev;
> > > >         struct reset_control *resetn;
> > > >         int ret;
> > > > @@ -392,6 +510,12 @@ static int rzg2l_irqc_init(struct device_node =
*node, struct device_node *parent)
> > > >         if (!rzg2l_irqc_data)
> > > >                 return -ENOMEM;
> > > >
> > > > +       match =3D of_match_node(rzg2l_irqc_matches, node);
> > > > +       if (match)
> > > > +               rzg2l_irqc_data->data =3D match->data;
> > > > +       else
> > > > +               rzg2l_irqc_data->data =3D &rzg2l_irqc_default_data;
> > >
> > > Instead of matching a second time, I'd rather add a second
> > > IRQCHIP_MATCH() entry with a different init function, passing the
> > > actual rzg2l_irqc_data pointer.
> > >
> > OK, or rather just pass true/false instead of rzg2l_irqc_of_data pointe=
r.?
>
> Yes, that would be fine for me, too.
> It all depends on whether you plan to add, or see a need for adding,
> more flags or other fields in the future (and even for flags, you could
> combine them in an unsigned long).
>
I'll keep the bool flag for now and update it  as  and when it grows.
I see future SoCs with a lot of other interrupts being supported by
this block.

Cheers,
Prabhakar

> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m6=
8k.org
>
> In personal conversations with technical people, I call myself a hacker. =
But
> when I'm talking to journalists I just say "programmer" or something like=
 that.
>                                 -- Linus Torvalds