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From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date: Thu, 1 Feb 2024 13:09:58 +0000
Message-ID: <CA+V-a8tJfJTEOkSP-F1B3Q7EO6Cu9ij88ceGJcXCQjTFneWxUA@mail.gmail.com>
Subject: Re: [PATCH 3/5] riscv: dts: renesas: r9a07g043f: Add IRQC node to
 RZ/Five SoC DTSI
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Thomas Gleixner <tglx@linutronix.de>, Rob Herring <robh+dt@kernel.org>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, 
	Magnus Damm <magnus.damm@gmail.com>, linux-renesas-soc@vger.kernel.org, 
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, 
	linux-kernel@vger.kernel.org, Biju Das <biju.das.jz@bp.renesas.com>, 
	Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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Hi Geert,

Thank you for the review.

On Tue, Jan 30, 2024 at 11:25=E2=80=AFAM Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, Jan 29, 2024 at 4:16=E2=80=AFPM Prabhakar <prabhakar.csengg@gmail=
com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add the IRQC node to RZ/Five (R9A07G043F) SoC DTSI.
>
> Thanks for your patch!
>
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> > --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > @@ -50,6 +50,82 @@ &soc {
> >         dma-noncoherent;
> >         interrupt-parent =3D <&plic>;
> >
> > +       irqc: interrupt-controller@110a0000 {
> > +               compatible =3D "renesas,r9a07g043f-irqc",
> > +                            "renesas,rzg2l-irqc";
> > +               reg =3D <0 0x110a0000 0 0x20000>;
> > +               #interrupt-cells =3D <2>;
> > +               #address-cells =3D <0>;
> > +               interrupt-controller;
> > +               interrupts =3D <SOC_PERIPHERAL_IRQ(0) IRQ_TYPE_LEVEL_HI=
GH>,
>
> As this is the RZ/Five-specific .dtsi file, and not the common base
> .dtsi, you could avoid using SOC_PERIPHERAL_IRQ() here.
> I am not sure what is most readable...
>
Ok, ill switch to the usual way here..

>+                            <SOC_PERIPHERAL_IRQ(25) IRQ_TYPE_EDGE_RISING>=
,
In RZ/Five HW manual this is documented as LEVEL_HIGH and RZ/G2UL this
is documented as EDGE. I ve internally asked for clarification with
the HW team. If it's the same for both the SoCs I'll move this node to
common SoC dtsi and just update the compat string in rz/five specific
dtsi.

Cheers,
Prabhakar

> The rest LGTM (pending interrupt names review comments).
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m6=
8k.org
>
> In personal conversations with technical people, I call myself a hacker. =
But
> when I'm talking to journalists I just say "programmer" or something like=
 that.
>                                 -- Linus Torvalds